一种用于1gb及以上dram的新型Pt电镀自对准堆叠电容器

1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325) Pub Date : 1999-06-14 DOI:10.1109/VLSIT.1999.799361

H. Horii, Byoung Taek Lee, Han Jin Lim, Suk Ho Joo, Chang Seok Kang, Cha Young Yoo, Hong Bae Park, Wan Don Kim, Sang In Lee, Moon Yong Lee

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引用次数: 3

摘要

我们首先开发了一种新的自对准电镀工艺，用于制造集成高介电电容器的Pt电极。电镀Pt填充120nm宽埋触点(BC)孔(纵横比2:1)。成功制备了直径210 nm、高650 nm的铂柱。镀底Pt溅射BST电容器的漏电流密度小于200 nA/cm/sup 2/ at /spl plusmn/1.5 V。在0 V下，40 nm厚BST薄膜的氧化当量厚度T/sub oxeq/和耗散系数分别为0.70 nm和0.0080 nm。

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A self-aligned stacked capacitor using novel Pt electroplating method for 1 Gbit DRAMs and beyond

We first developed a novel self-aligned electroplating process to fabricate Pt electrodes for integrated high-dielectric capacitors. Electroplated Pt filled 120 nm-wide buried contact (BC) holes (aspect ratio 2:1). Pt pillars of 210 nm diameter and 650 nm height were successfully fabricated. The leakage current density of sputtered BST capacitors using electroplated bottom Pt was less than 200 nA/cm/sup 2/ at /spl plusmn/1.5 V. The oxide-equivalent thickness T/sub oxeq/ and dissipation factor of 40 nm-thick BST films were 0.70 nm and 0.0080 at 0 V, respectively.

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1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)

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