Substrate enhanced gate current: device design and temperature impact and disturbs in programming flash memories with negative body bias

Abstract

Substrate negative polarization enhances gate current in submicron MOSFETs, improving two different hot carrier mechanisms (Esseni et al., 1998): CHEI (channel hot electron injection) and CISEI (channel induced secondary electron injection) (Bude et al, 1995). This effect is of particular interest in flash memory research, because it allows low power programming. In this paper, we first identify which of the two mechanisms prevails for each bias scheme, with or without body bias. Then, we analyse experimentally the impact of some device parameters and temperature on the total gate current, identifying the different trends of CHEI and CISEI. Finally, the programming disturbs are evaluated. Substrate polarization could worsen the electrical stress of the cells which belong to the same word line or bit line of the selected one, since the substrate is shared by the whole array.