A 0.22 /spl mu/m CMOS-SOI technology with a Cu BEOL

1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325) Pub Date : 1999-06-14 DOI:10.1109/VLSIT.1999.799317

A. Ajmera, J. Sleight, F. Assaderaghi, R. Bolam, A. Bryant, M. Coffey, H. Hovel, J. Lasky, E. Leobandung, W. Rausch, D. Sadana, D. Schepis, L. Wagner, K. Wu, B. Davari, G. Shahidi

引用次数: 5

Abstract

A 0.22 /spl mu/m CMOS on SOI technology, using a nonfully depleted device, is developed. This technology uses the same gate lithography and metallization as a comparable bulk technology, but offers a 20-35% higher performance at the chip level. Furthermore, it offers the complete device and circuit elements used in bulk CMOS (low V/sub T/ device, ESD diode, and decoupling capacitance). This technology was applied to a 64 b RISC processor.

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一个0.22 /spl mu/m CMOS-SOI技术与Cu BEOL

采用非完全耗尽器件，在SOI上开发了0.22 /spl μ m CMOS。该技术使用与同类批量技术相同的栅极光刻和金属化技术，但在芯片级提供20-35%的高性能。此外，它还提供了用于批量CMOS的完整器件和电路元件(低V/sub /器件，ESD二极管和去耦电容)。该技术已应用于64b RISC处理器。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)

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