器件和可靠性高k Al/sub 2/O/sub 3/栅极电介质具有良好的迁移率和低D/sub it/

1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325) Pub Date : 1999-06-14 DOI:10.1109/VLSIT.1999.799380

A. Chin, C. Liao, C.H. Lu, W. Chen, C. Tsai

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引用次数: 25

摘要

我们报道了一种非常简单的工艺，用于CMOS技术制备Al/sub 2/O/sub 3/栅极电介质，其k(9.0 ~ 9.8)大于Si/sub 3/N/sub 4/。Al/sub 2/O/sub 3/是由热蒸发的Al直接氧化形成的。48 /spl的Aring/ Al/sub 2/O/sub 3/比等效的21 /spl的Aring/ SiO/sub 2/的泄漏电流低7个数量级。界面密度为1/ sp1倍/10/sup 11/ eVcm/sup -2/，且电子迁移率与热SiO/sub -2/兼容，证明了Al/sub -2/ O/sub - 3/-Si界面良好。在2.5 V应力作用10000 s后，其应力诱发漏电流(SILC)较小，可靠性较好。

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Device and reliability of high-k Al/sub 2/O/sub 3/ gate dielectric with good mobility and low D/sub it/

We report a very simple process to fabricate Al/sub 2/O/sub 3/ gate dielectric for CMOS technology with k (9.0 to 9.8) greater than Si/sub 3/N/sub 4/. Al/sub 2/O/sub 3/ is formed by direct oxidation from thermally evaporated Al. The 48 /spl Aring/ Al/sub 2/O/sub 3/ has /spl sim/7 orders lower leakage current than equivalent 21 /spl Aring/ SiO/sub 2/. A good Al/sub 2/O/sub 3/-Si interface was evidenced by the low interface density of 1/spl times/10/sup 11/ eVcm/sup -2/ and compatible electron mobility with thermal SiO/sub 2/. Good reliability is measured from the small stress induced leakage current (SILC) after 2.5 V stress for 10,000 s.

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1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)

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