采用低压CVD-WN圆柱存储节点的高可靠性MIM电容技术，用于0.12 /spl mu/m级嵌入式DRAM

1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325) Pub Date : 1999-06-14 DOI:10.1109/VLSIT.1999.799329

S. Kamiyama, J. M. Drynan, Y. Takaishi, K. Koyama

{"title":"采用低压CVD-WN圆柱存储节点的高可靠性MIM电容技术，用于0.12 /spl mu/m级嵌入式DRAM","authors":"S. Kamiyama, J. M. Drynan, Y. Takaishi, K. Koyama","doi":"10.1109/VLSIT.1999.799329","DOIUrl":null,"url":null,"abstract":"A metal-insulator-metal (MIM) capacitor process technology has been developed using highly reliable ultra-thin Ta/sub 2/O/sub 5/ capacitors with low pressure CVD-WN cylinder storage-nodes for 0.12 /spl mu/m-scale embedded DRAMs. The CVD-WN films using WF/sub 6/ and NF/sub 3/ gases have excellent characteristics with respect to surface morphology and step coverage in comparison with CVD-W films. As a result, the cell capacitance with CVD-WN cylinder storage-nodes is increased to 1.5 times as large as that of CVD-W cylinder storage-nodes. The CVD-WN cylinder capacitors can realize a 30 fF/cell capacitance with 0.6 /spl mu/m-height storage-nodes in an area of 0.25/spl times/0.5 /spl mu/m/sup 2/.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Highly reliable MIM capacitor technology using low pressure CVD-WN cylinder storage-node for 0.12 /spl mu/m-scale embedded DRAM\",\"authors\":\"S. Kamiyama, J. M. Drynan, Y. Takaishi, K. Koyama\",\"doi\":\"10.1109/VLSIT.1999.799329\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A metal-insulator-metal (MIM) capacitor process technology has been developed using highly reliable ultra-thin Ta/sub 2/O/sub 5/ capacitors with low pressure CVD-WN cylinder storage-nodes for 0.12 /spl mu/m-scale embedded DRAMs. The CVD-WN films using WF/sub 6/ and NF/sub 3/ gases have excellent characteristics with respect to surface morphology and step coverage in comparison with CVD-W films. As a result, the cell capacitance with CVD-WN cylinder storage-nodes is increased to 1.5 times as large as that of CVD-W cylinder storage-nodes. The CVD-WN cylinder capacitors can realize a 30 fF/cell capacitance with 0.6 /spl mu/m-height storage-nodes in an area of 0.25/spl times/0.5 /spl mu/m/sup 2/.\",\"PeriodicalId\":171010,\"journal\":{\"name\":\"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)\",\"volume\":\"47 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.1999.799329\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1999.799329","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 6

摘要

采用具有低压CVD-WN圆柱存储节点的超薄钽/亚2/O/亚5/电容器，开发了一种用于0.12 /spl mu/m级嵌入式dram的金属-绝缘体-金属(MIM)电容器工艺技术。与CVD-W膜相比，使用WF/sub - 6/和NF/sub - 3/气体制备的CVD-WN膜在表面形貌和台阶覆盖方面具有优异的特性。结果表明，采用CVD-WN柱状存储节点的电池容量是采用CVD-W柱状存储节点的电池容量的1.5倍。CVD-WN圆柱形电容器在0.25/spl次/0.5 /spl mu/m/sup 2/ m2的面积上，以0.6 /spl mu/m-高的存储节点可实现30 fF/cell的电容。

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Highly reliable MIM capacitor technology using low pressure CVD-WN cylinder storage-node for 0.12 /spl mu/m-scale embedded DRAM

A metal-insulator-metal (MIM) capacitor process technology has been developed using highly reliable ultra-thin Ta/sub 2/O/sub 5/ capacitors with low pressure CVD-WN cylinder storage-nodes for 0.12 /spl mu/m-scale embedded DRAMs. The CVD-WN films using WF/sub 6/ and NF/sub 3/ gases have excellent characteristics with respect to surface morphology and step coverage in comparison with CVD-W films. As a result, the cell capacitance with CVD-WN cylinder storage-nodes is increased to 1.5 times as large as that of CVD-W cylinder storage-nodes. The CVD-WN cylinder capacitors can realize a 30 fF/cell capacitance with 0.6 /spl mu/m-height storage-nodes in an area of 0.25/spl times/0.5 /spl mu/m/sup 2/.

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1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)

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