2016 IEEE International 3D Systems Integration Conference (3DIC)最新文献

Analog-digital partitioning and coupling in 3D-IC for RF applications 用于射频应用的3D-IC中的模数划分和耦合

2016 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2016-11-01 DOI: 10.1109/3DIC.2016.7970011

G. Yahalom, S. Ho, Alice Wang, U. Ko, A. Chandrakasan

引用次数: 3

3 Dimensional stacked pixel detector and sensor technology using less than 3-μmφ robust bump junctions 采用小于3 μmφ鲁棒凹凸结的三维堆叠像素探测器和传感器技术

2016 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2016-11-01 DOI: 10.1109/3DIC.2016.7970029

M. Motoyoshi, K. Yanagimura, T. Fushimi, Junichi Takanohashi, M. Murugesan, M. Aoyagi, M. Koyanagi

引用次数: 1

3DIP: An iterative partitioning tool for monolithic 3D IC 3DIP:用于单片3D集成电路的迭代划分工具

2016 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2016-11-01 DOI: 10.1109/3DIC.2016.7970013

G. Berhault, M. Brocard, S. Thuries, François Galea, Lilia Zaourar

引用次数: 7

Novel inter layer dielectric and thermal TSV material for enhanced heat mitigation in 3-D IC 新型层间介质和热TSV材料增强了三维集成电路的散热

2016 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2016-11-01 DOI: 10.1109/3DIC.2016.7970005

K. Khurram, A. Panigrahi, Satish Bonam, Om Krishan Singh, S. Singh

引用次数: 1

Wet cleaning process for high-yield via-last TSV formation 湿法清洗法制备高产量的过尾TSV

2016 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2016-11-01 DOI: 10.1109/3DIC.2016.7970026

N. Watanabe, H. Shimamoto, K. Kikuchi, M. Aoyagi, H. Kikuchi, A. Yanagisawa, Akio Nakamura

{"title":"Wet cleaning process for high-yield via-last TSV formation","authors":"N. Watanabe, H. Shimamoto, K. Kikuchi, M. Aoyagi, H. Kikuchi, A. Yanagisawa, Akio Nakamura","doi":"10.1109/3DIC.2016.7970026","DOIUrl":"https://doi.org/10.1109/3DIC.2016.7970026","url":null,"abstract":"The backside via-last through silicon via (TSV) process is a simple and cost-effective approach for three-dimensional integration. However, it has two problems: (1) the notching near the bottom corners of TSVs and (2) the reaction product generated by the etchback step. To overcome these problems and increase TSV yield, we previously proposed a via-last TSV process using notchless Si etching and wet cleaning of the first metal layer. In this process, the notching was suppressed by optimizing the deep Si etching conditions. In addition, wet cleaning of the first metal layer was performed with a novel cleaning solution to remove reaction products on the first metal layer (which was generated by the etchback step) and create good electrical contact between the TSVs and the first metal layer. In this study, we investigated the characteristics of a novel solution used in the wet cleaning process. The wettability between the novel solution and the TSV liner oxide was very good. The cleaning performance of the novel solution was high while the etching rate of the first metal was very small.","PeriodicalId":166245,"journal":{"name":"2016 IEEE International 3D Systems Integration Conference (3DIC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114870716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Considerations of TSV effects on next-generation super-high-speed transmission and power integrity design for 300A-class 2.5D and 3D package integration 300a级2.5D和3D封装集成中TSV对下一代超高速传输和电源完整性设计的影响

2016 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2016-11-01 DOI: 10.1109/3DIC.2016.7969995

Makoto Suwada, Kazuhiro Kanai

引用次数: 0

Continuity and reliability assessment of a scalable 3×50μm and 2×40μm via-middle TSV module 可扩展3×50μm和2×40μm中路TSV模块的连续性和可靠性评估

2016 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2016-11-01 DOI: 10.1109/3DIC.2016.7970001

S. V. Huylenbroeck, Yunlong Li, M. Stucchi, L. Bogaerts, J. D. Vos, G. Beyer, E. Beyne, M. Brouri, P. Nalla, S. Gopinath, Matthew Thorum, Joe Richardson, Jengyi Yu

{"title":"Continuity and reliability assessment of a scalable 3×50μm and 2×40μm via-middle TSV module","authors":"S. V. Huylenbroeck, Yunlong Li, M. Stucchi, L. Bogaerts, J. D. Vos, G. Beyer, E. Beyne, M. Brouri, P. Nalla, S. Gopinath, Matthew Thorum, Joe Richardson, Jengyi Yu","doi":"10.1109/3DIC.2016.7970001","DOIUrl":"https://doi.org/10.1109/3DIC.2016.7970001","url":null,"abstract":"An advanced TSV metallization scheme, featuring a high conformal ALD oxide liner, a thermal ALD WN barrier, an electroless NiB platable seed and a high throughput copper ECD filling is presented. Because of the high conformality of the WN barrier and NiB seed, very thin layers can be deposited, reducing the manufacturing cost significantly, while still guaranteeing continuous barrier/seed layers all along the TSV sidewall to the bottom of the TSV. 3 × 50μm via-middle wafers, processed with this metallization scheme, are further processed through the thinning module, by using temporary bonded carriers, the backside passivation module and a copper RDL module by using a semi-additive process. The TSV resistance is measured between the 5μm thick RDL copper layer at the back side and the METPASS aluminum layer at the wafer front side. Low spread and high yield is obtained on the resistance data distribution of both single kelvin and daisy chain structures. The same metallization scheme is successfully scaled to a 2μm diameter and 40μm deep via-middle module. The conformal deposition of the barrier and the seed layer enables further scaling down to aspect ratio 20:1 through silicon via's with 5μm pitch, still ensuring the void-free bottom up copper fill by electroplating. The integrity of the liner/barrier system against Cu diffusion from TSV to silicon has been verified using the established controlled I-V method. Field acceleration factors, extracted in both copper-confined and copper-driven regime, indicate good TDDB reliability of this advanced 2 × 40μm TSV middle module.","PeriodicalId":166245,"journal":{"name":"2016 IEEE International 3D Systems Integration Conference (3DIC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125067375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

3D floorplan representations: Corner links and partial order 三维平面图表示:角链接和部分顺序

2016 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2016-11-01 DOI: 10.1109/3DIC.2016.7970023

F. Qiao, Ilgweon Kang, D. Kane, Evangeline F. Y. Young, Chung-Kuan Cheng, R. Graham

引用次数: 1

Through-substrate via (TSV) with embedded capacitor as an on-chip energy storage element 通过衬底通孔(TSV)嵌入电容器作为片上储能元件

2016 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2016-11-01 DOI: 10.1109/3DIC.2016.7970003

Ye Lin, C. S. Tan

引用次数: 7

A front-illuminated stacked global-shutter CMOS image sensor with multiple chip-on-chip integration 一种具有多片对片集成的前置照明堆叠全局快门CMOS图像传感器

2016 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2016-11-01 DOI: 10.1109/3DIC.2016.7970033

Kentaro Akiyama, Y. Oike, Y. Kitano, Junichiro Fjimagari, Wakiyama Satoru, Y. Sakano, T. Toyama, H. Iwamoto, T. Ezaki, Takuya Nakamura, Tetsunori Imaizumi, Nonaka Yasuhiro

引用次数: 1