2016 IEEE International 3D Systems Integration Conference (3DIC)最新文献_第2页

High density backside tungsten TSV for 3D stacked ICs 用于3D堆叠ic的高密度背面钨质TSV

2016 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2016-11-01 DOI: 10.1109/3DIC.2016.7970020

Reynard Blasa, B. Mattis, D. Martini, Sidi Lanee, C. Petteway, Sangki Hong, Kangsoo Yi

引用次数: 1

Physical design of a 3D-stacked heterogeneous multi-core processor 3d堆叠异构多核处理器的物理设计

2016 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2016-11-01 DOI: 10.1109/3DIC.2016.7970036

Randy Widialaksono, Rangeen Basu Roy Chowdhury, Zhenqian Zhang, J. Schabel, S. Lipa, E. Rotenberg, W. R. Davis, P. Franzon

引用次数: 4

Low cost polyimide liner formation with vacuum-assisted spin coating for through-silicon-vias 低成本聚酰亚胺衬垫形成与真空辅助旋转涂层的硅通孔

2016 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2016-11-01 DOI: 10.1109/3DIC.2016.7970040

Yangyang Yan, Ziyue Zhang, Zhiqiang Cheng, Lingfeng Zhou, Zhiming Chen, Yingtao Ding

{"title":"Low cost polyimide liner formation with vacuum-assisted spin coating for through-silicon-vias","authors":"Yangyang Yan, Ziyue Zhang, Zhiqiang Cheng, Lingfeng Zhou, Zhiming Chen, Yingtao Ding","doi":"10.1109/3DIC.2016.7970040","DOIUrl":"https://doi.org/10.1109/3DIC.2016.7970040","url":null,"abstract":"Three-dimensional (3-D) integration with through-silicon-vias(TSVs) has been laid high expectations in overcoming further miniaturization obstacles faced by conventional 2-D integrated circuits (ICs) and solving compatibility problems of system integration among heterogeneous chips. We have proposed a simple but feasible process named “vacuum-assisted spin coating” for the fabrication of high aspect-ratio TSVs with polyimide (PI) liners at low cost to reduce its parasitic capacitance while increase its thermomechanical reliability. In this paper, the mechanism of the technique, liner thickness controllability, impacts of PI liner on TSV keep-out zone (KOZ), and its adaptability to “via-last”3-D integration paradigm were addressed. Minimum step coverage of PI liner after the second coating procedure showed an increase from 32.9% to 47.6%, indicating more conformal PI liners were obtained. A 3-D finite element analysis was also employed to check KOZ of TSVs with PI/SiO2 liners on P-type Si with [100] and [110] device alignment. By employing PI liners, KOZ sizes were seen a reduction of 24.2% and 25.8% on [100] and [110] direction, respectively.","PeriodicalId":166245,"journal":{"name":"2016 IEEE International 3D Systems Integration Conference (3DIC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125326236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Front-side mid-level Tungsten TSV integration for high-density 3D applications 前端中级钨TSV集成高密度3D应用

2016 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2016-11-01 DOI: 10.1109/3DIC.2016.7970008

B. Mattis, L. Soirez, Catherine Bullock, D. Martini, Sara Jensen, J. Levy, Adam Jones

引用次数: 1

Improved noise coupling performance using optimized Teflon liner with different TSV structures for 3D IC integration 采用优化的Teflon衬垫和不同的TSV结构，改善了3D集成电路的噪声耦合性能

2016 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2016-11-01 DOI: 10.1109/3DIC.2016.7970021

S. Patil, A. Panigrahi, Satish Bonam, C. H. Kumar, Om Krishan Singh, S. Singh

引用次数: 3

Improving the integrity of Ti barrier layer in Cu-TSVs through self-formed TiSix for via-last TSV technology 通过自形成TiSix提高cu -TSV中Ti势垒层的完整性

2016 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2016-11-01 DOI: 10.1109/3DIC.2016.7970017

M. Murugesan, J. Bea, T. Fukushima, M. Motoyoshi, Tetsu Tanaka, M. Koyanagi

引用次数: 0

Low temperature CMOS compatible Cu-Cu thermo-compression bonding with constantan alloy passivation for 3D IC integration 低温CMOS兼容Cu-Cu热压键合与康坦合金钝化用于3D集成电路

2016 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2016-11-01 DOI: 10.1109/3DIC.2016.7970019

A. Panigrahi, Satish Bonam, Tamal Ghosh, S. Vanjari, S. Singh

{"title":"Low temperature CMOS compatible Cu-Cu thermo-compression bonding with constantan alloy passivation for 3D IC integration","authors":"A. Panigrahi, Satish Bonam, Tamal Ghosh, S. Vanjari, S. Singh","doi":"10.1109/3DIC.2016.7970019","DOIUrl":"https://doi.org/10.1109/3DIC.2016.7970019","url":null,"abstract":"In this paper, we report low temperature wafer level Cu-Cu thermo-compression bonding using an ultra-thin Copper — Nickel based alloy layer, constantan as passivation layer. Major bottlenecks in achieving low temperature and low pressure bonding are surface oxidation and roughness. Constantan alloy on Cu surface has a dual role of preventing Cu surface from oxidation and reduces the surface roughness. Passivation reduces the bonding temperature as it prevents copper surface from oxidation. In this endeavor, constantan alloy passivation thickness was optimized by varying thickness of constantan layer on Cu surface and studied the effect of surface roughness by performing AFM analysis. Simultaneously surface passivation was studied using Secondary Ion Mass Spectroscopy (SIMS) depth profiling. The optimum constantan passivation thickness is found to be 2 nm for achieving wafer level Cu-Cu bonding at temperature as low as 150 ˚C at constant contact force of 4.5 kN (5 bar). Our optimized result yielded a very good bond strength of 152 MPa which compared well with the available literatures.","PeriodicalId":166245,"journal":{"name":"2016 IEEE International 3D Systems Integration Conference (3DIC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133145278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and analysis of on-interposer active power distribution network for an efficient simultaneous switching noise suppression in 2.5D IC 2.5D集成电路中有效同时抑制开关噪声的中间有功配电网络设计与分析

2016 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2016-11-01 DOI: 10.1109/3DIC.2016.7970006

Subin Kim, Youngwoo Kim, Kyungjun Cho, Jinwook Song, Joungho Kim

{"title":"Design and analysis of on-interposer active power distribution network for an efficient simultaneous switching noise suppression in 2.5D IC","authors":"Subin Kim, Youngwoo Kim, Kyungjun Cho, Jinwook Song, Joungho Kim","doi":"10.1109/3DIC.2016.7970006","DOIUrl":"https://doi.org/10.1109/3DIC.2016.7970006","url":null,"abstract":"Simultaneous switching noise (SSN) occurs when clock synchronized core circuits switch simultaneously. Furthermore, a huge amount of the SSN generated by simultaneous switching current (SSC) with high power distribution network (PDN) impedance at anti-resonance can cause electromagnetic interference (EMI) problems and logic failure. In multi-core processors, the spectrum of SSC is varied by power management techniques such as dynamic voltage and frequency scaling (DVFS). However, conventional PDN cannot respond to these various SSC spectrum due to its passive characteristics. In this paper, an externally controllable on-interposer decoupling capacitance scheme, namely on-interposer active PDN, is proposed to efficiently suppress the SSN in 2.5D IC. The proposed scheme designed on the active silicon interposer can shift the frequency of the PDN anti-resonance peak with on-interposer decoupling capacitors controlled by external switching operation based on monitored SSN voltage. To verify the proposed scheme, it is modeled and analyzed in the frequency and time domain simulations. We have demonstrated that an efficient SSN suppression is achieved by obtaining the optimum on-interposer decoupling capacitance and the maximum ratio of the SSN suppression was 31.3%.","PeriodicalId":166245,"journal":{"name":"2016 IEEE International 3D Systems Integration Conference (3DIC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127880895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Analysis of graphene and CNT based finned TTSV and spreaders for thermal management in 3D IC 基于石墨烯和碳纳米管的翅片TTSV和散热片在3D集成电路中的热管理分析

2016 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2016-11-01 DOI: 10.1109/3DIC.2016.7970000

Suraj Singh, A. Panigrahi, Om Krishan Singh, S. Singh

引用次数: 8

Importance of alignment control during permanent bonding and its impact on via-last alignment for high density 3D interconnects 高密度三维互连永接过程中对中控制的重要性及其对过孔对中的影响

2016 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2016-11-01 DOI: 10.1109/3DIC.2016.7970002

J. D. Vos, Lan Peng, A. Phommahaxay, Joost Van Ongeval, Andy Miller, E. Beyne, F. Kurz, Thomas Wagenleiter, M. Wimplinger, T. Uhrmann

引用次数: 13