Importance of alignment control during permanent bonding and its impact on via-last alignment for high density 3D interconnects

Abstract

As the density of 3D interconnects is increasing exponentially when scaling to lower levels of the interconnect wiring, in most cases 3D interconnect pitches of 5 μm and below will be required. Dielectric wafer to wafer bonding with via last integration can offer these interconnect densities. Wafer-to-wafer alignment and its impact on via last alignment are discussed. By taking into account current alignment tolerances, via last diameters of 1μm enable 2μm pitch TSV interconnection densities. For further scaling the TSV pitch, lower wafer to wafer bonding alignment tolerance are required. Today the best wafer-to-wafer overlay accuracy is around 400nm, but developments are ongoing to reduce this tolerance further to 200nm.