Design and analysis of on-interposer active power distribution network for an efficient simultaneous switching noise suppression in 2.5D IC

Abstract

Simultaneous switching noise (SSN) occurs when clock synchronized core circuits switch simultaneously. Furthermore, a huge amount of the SSN generated by simultaneous switching current (SSC) with high power distribution network (PDN) impedance at anti-resonance can cause electromagnetic interference (EMI) problems and logic failure. In multi-core processors, the spectrum of SSC is varied by power management techniques such as dynamic voltage and frequency scaling (DVFS). However, conventional PDN cannot respond to these various SSC spectrum due to its passive characteristics. In this paper, an externally controllable on-interposer decoupling capacitance scheme, namely on-interposer active PDN, is proposed to efficiently suppress the SSN in 2.5D IC. The proposed scheme designed on the active silicon interposer can shift the frequency of the PDN anti-resonance peak with on-interposer decoupling capacitors controlled by external switching operation based on monitored SSN voltage. To verify the proposed scheme, it is modeled and analyzed in the frequency and time domain simulations. We have demonstrated that an efficient SSN suppression is achieved by obtaining the optimum on-interposer decoupling capacitance and the maximum ratio of the SSN suppression was 31.3%.