High density backside tungsten TSV for 3D stacked ICs

Abstract

In this paper we will discuss a method of fabricating a 0.8um and 1.2um diameter, 10um deep tungsten through-silicon-vias (TSV) from the backside of a 200mm silicon wafer at 4um and 2um pitches. These high-density tungsten TSVs connect to a thin copper backend, such as a metal 1 layer (M1) which can be as thin as 1000Å. We've applied this technology on a CMOS wafer from a high volume foundry and inserted our TSV-last module to enable wafer stacking, which is one aspect of 3D integration. Early tests on 1.2um diameter TSV, 4um pitch, 50000-element chain indicate wafer level yields of > 90% @ < 3 Ohms per contact. This process successfully demonstrates a high density, backside tungsten TSV integration with encouraging via chain yield. The process flow outlined in this paper can be utilized to enable 3D integration for two or more wafers from different foundries or different technology nodes.