Low cost polyimide liner formation with vacuum-assisted spin coating for through-silicon-vias

Abstract

Three-dimensional (3-D) integration with through-silicon-vias(TSVs) has been laid high expectations in overcoming further miniaturization obstacles faced by conventional 2-D integrated circuits (ICs) and solving compatibility problems of system integration among heterogeneous chips. We have proposed a simple but feasible process named “vacuum-assisted spin coating” for the fabrication of high aspect-ratio TSVs with polyimide (PI) liners at low cost to reduce its parasitic capacitance while increase its thermomechanical reliability. In this paper, the mechanism of the technique, liner thickness controllability, impacts of PI liner on TSV keep-out zone (KOZ), and its adaptability to “via-last”3-D integration paradigm were addressed. Minimum step coverage of PI liner after the second coating procedure showed an increase from 32.9% to 47.6%, indicating more conformal PI liners were obtained. A 3-D finite element analysis was also employed to check KOZ of TSVs with PI/SiO2 liners on P-type Si with [100] and [110] device alignment. By employing PI liners, KOZ sizes were seen a reduction of 24.2% and 25.8% on [100] and [110] direction, respectively.