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A 3D multi-layer CMOS-RRAM accelerator for neural network 用于神经网络的三维多层CMOS-RRAM加速器
2016 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2016-11-01 DOI: 10.1109/3DIC.2016.7970014
Hantao Huang, Leibin Ni, Yuhao Wang, Hao Yu, Zongwei Wang, Yimao Cai, Ru Huang
{"title":"A 3D multi-layer CMOS-RRAM accelerator for neural network","authors":"Hantao Huang, Leibin Ni, Yuhao Wang, Hao Yu, Zongwei Wang, Yimao Cai, Ru Huang","doi":"10.1109/3DIC.2016.7970014","DOIUrl":"https://doi.org/10.1109/3DIC.2016.7970014","url":null,"abstract":"Incremental machine learning is required for future real-time data analytics. This paper introduces a 3D multilayer CMOS-RRAM accelerator for an incremental least-squares based learning on neural network. Given input of buffered data hold on the layer of a RRAM memory, intensive matrix-vector multiplication can be firstly accelerated on the layer of a digitized RRAM-crossbar. The remaining incremental leastsquares algorithmic operations for feature extraction and classifier training can be accelerated on the layer of CMOS ASIC, using an incremental Cholesky factorization accelerator realized with consideration of parallelism and pipeline. Experiment results have shown that such a 3D accelerator can significantly reduce training time with acceptable accuracy. Compared to 3D-CMOS-ASIC implementation, it can achieve 1.28x smaller area, 2.05x faster runtime and 12.4x energy reduction. Compared to GPU implementation, our work shows 3.07x speed-up and 162.86x energy-saving.","PeriodicalId":166245,"journal":{"name":"2016 IEEE International 3D Systems Integration Conference (3DIC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128310892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Copper TSV-based die-level via-last 3D integration process with parylene-C adhesive bonding technique 基于铜tsv的模具级过孔三维集成工艺与聚苯乙烯- c粘接技术
2016 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2016-11-01 DOI: 10.1109/3DIC.2016.7970016
S. K. Eroglu, W. Y. Choo, Y. Leblebici
{"title":"Copper TSV-based die-level via-last 3D integration process with parylene-C adhesive bonding technique","authors":"S. K. Eroglu, W. Y. Choo, Y. Leblebici","doi":"10.1109/3DIC.2016.7970016","DOIUrl":"https://doi.org/10.1109/3DIC.2016.7970016","url":null,"abstract":"This paper presents a die-level post-CMOS processing protocol for multi-layer homogeneous 3D integration with adhesive bonding technique using parylene-C as an intermediate bonding layer and sidewall passivation material. This protocol was used to fabricate 4-layer CMOS memory chip stacks, which were then packaged and tested using time domain reflectometry (TDR) measurement technique. The results have showed that the characteristic inductance values were improved for 3D integrated memory chips due to the elimination of bonding wires.","PeriodicalId":166245,"journal":{"name":"2016 IEEE International 3D Systems Integration Conference (3DIC)","volume":"178 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115411290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
New concept of TSV formation methodology using Directed Self-Assembly (DSA) 基于定向自组装(DSA)的TSV形成方法新概念
2016 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2016-11-01 DOI: 10.1109/3DIC.2016.7970022
T. Fukushima, M. Murugesan, Shin-ichi Ohsaki, H. Hashimoto, J. Bea, Kang-wook Lee, Tetsu Tanaka, M. Koyanagi
{"title":"New concept of TSV formation methodology using Directed Self-Assembly (DSA)","authors":"T. Fukushima, M. Murugesan, Shin-ichi Ohsaki, H. Hashimoto, J. Bea, Kang-wook Lee, Tetsu Tanaka, M. Koyanagi","doi":"10.1109/3DIC.2016.7970022","DOIUrl":"https://doi.org/10.1109/3DIC.2016.7970022","url":null,"abstract":"A new TSV formation methodology based on advanced Directed Self-Assembly (DSA) with nanocomposites consisting of nano metal particles and block-co-polymers is proposed in this paper. Cylindrical nano-ordered structures are formed in Si deep holes through phase separation of polystyrene-block-poly methyl methacrylate polymers (PS-b-PMMA). The impact of molecular weight of the polymers, composition (PS/PMMA ratio), and phase separation temperature on the morphologies is discussed. In addition, simulation results using Self-Consistent Field (SCF) theory are introduced to make fine-pitch TSV.","PeriodicalId":166245,"journal":{"name":"2016 IEEE International 3D Systems Integration Conference (3DIC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123376624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The impact of 3D stacking on GPU-accelerated deep neural networks: An experimental study 三维叠加对gpu加速深度神经网络影响的实验研究
2016 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2016-11-01 DOI: 10.1109/3DIC.2016.7970018
W. Wahby, Thomas E. Sarvey, Hardik Sharma, H. Esmaeilzadeh, M. Bakir
{"title":"The impact of 3D stacking on GPU-accelerated deep neural networks: An experimental study","authors":"W. Wahby, Thomas E. Sarvey, Hardik Sharma, H. Esmaeilzadeh, M. Bakir","doi":"10.1109/3DIC.2016.7970018","DOIUrl":"https://doi.org/10.1109/3DIC.2016.7970018","url":null,"abstract":"In this work, we present a two-tier air-cooled thermal testbed composed of an NVIDIA Tesla K40 GPU and a heater/thermometer top die. The top die has four independently-controllable heaters, which can emulate a wide range of components, ranging from low power memory to high-performance multi-core processor cores. The performance and temperature of the bottom-tier GPU on several deep neural network workloads is investigated as a function of increasing top-die power dissipation, and the implications for 3DIC cooling are discussed.","PeriodicalId":166245,"journal":{"name":"2016 IEEE International 3D Systems Integration Conference (3DIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129986692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
ITAC: A complete 3D integration test platform ITAC:完整的3D集成测试平台
2016 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2016-11-01 DOI: 10.1109/3DIC.2016.7970012
D. Lattard, L. Arnaud, A. Garnier, N. Bresson, F. Bana, R. Segaud, A. Jouve, H. Jacquinot, S. Moreau, Karim Azizi-Mourier, C. Chantre, P. Vivet, G. Pillonnet, F. Casset, F. Ponthenier, A. Farcy, S. Lhostis, J. Michailos, A. Arriordaz, S. Chéramy
{"title":"ITAC: A complete 3D integration test platform","authors":"D. Lattard, L. Arnaud, A. Garnier, N. Bresson, F. Bana, R. Segaud, A. Jouve, H. Jacquinot, S. Moreau, Karim Azizi-Mourier, C. Chantre, P. Vivet, G. Pillonnet, F. Casset, F. Ponthenier, A. Farcy, S. Lhostis, J. Michailos, A. Arriordaz, S. Chéramy","doi":"10.1109/3DIC.2016.7970012","DOIUrl":"https://doi.org/10.1109/3DIC.2016.7970012","url":null,"abstract":"System integration takes benefit from 3D stacking technology in a wide range of applications such as smart imagers, photonic, wide I/O memories and high-performance computing. The 700 mm2 ITAC 3D integration test platform contains a set of “Integrated Technological and Application Circuits” for process development, electrical and RF characterization, reliability, die stacking, warpage and underfilling studies, DC-DC converter and IntAct chip which is the full application chip. After a brief presentation of the targeted high performance computing application. The contributions integrated in the test platform are described with a particular focus on the 10 μm diameter 20 μm pitch die-to-die interconnects which is the key technology of the 3D stack. These test vehicles have been embedded on the same silicon to secure the application chip at all the steps from technology development to assembly and test.","PeriodicalId":166245,"journal":{"name":"2016 IEEE International 3D Systems Integration Conference (3DIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122958846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Die to wafer 3D stacking for below 10um pitch microbumps 对于小于10um间距的微凸点，晶圆对晶圆的3D堆叠
2016 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2016-11-01 DOI: 10.1109/3DIC.2016.7969993
J. Derakhshandeh, L. Hou, I. D. Preter, C. Gerets, S. Suhard, V. Dubey, G. Jamieson, F. Inoue, T. Webers, P. Bex, G. Capuz, E. Beyne, J. Slabbekoorn, Teng Wang, A. Jourdain, G. Beyer, K. Rebibis, Andy Miller
{"title":"Die to wafer 3D stacking for below 10um pitch microbumps","authors":"J. Derakhshandeh, L. Hou, I. D. Preter, C. Gerets, S. Suhard, V. Dubey, G. Jamieson, F. Inoue, T. Webers, P. Bex, G. Capuz, E. Beyne, J. Slabbekoorn, Teng Wang, A. Jourdain, G. Beyer, K. Rebibis, Andy Miller","doi":"10.1109/3DIC.2016.7969993","DOIUrl":"https://doi.org/10.1109/3DIC.2016.7969993","url":null,"abstract":"Processing of bump-less or embedded microbumps is introduced in this paper as an approach which enables scaling microbumps for below 10um pitches. Landing wafer is standard damascene process and in top wafer bumps are embedded in a soft backed polymer. Later during thermo-compression bonding this polymer is cured to bond two chips together. Process flow and results of TC bonding is discussed in this paper.","PeriodicalId":166245,"journal":{"name":"2016 IEEE International 3D Systems Integration Conference (3DIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126048127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Drastic reduction of keep-out-zone in 3D-IC by local stress suppression with negative-CTE filler 通过使用负cte填充物抑制局部应力，大幅度减少3D-IC的隔离区
2016 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2016-11-01 DOI: 10.1109/3DIC.2016.7970031
H. Kino, T. Fukushima, Tetsu Tanaka
{"title":"Drastic reduction of keep-out-zone in 3D-IC by local stress suppression with negative-CTE filler","authors":"H. Kino, T. Fukushima, Tetsu Tanaka","doi":"10.1109/3DIC.2016.7970031","DOIUrl":"https://doi.org/10.1109/3DIC.2016.7970031","url":null,"abstract":"Three-dimensional IC (3D IC) is a promising method to enhance IC performance. Conventional 3D ICs consist of vertically stacked several thin IC chips those are electrically connected with lots of through-Si vias (TSVs) and metal microbumps. Metal microbumps are surrounded by organic adhesive. An epoxy-based material, so-called underfill, has been widely used to fill the gap between several chips. In general, coefficient of thermal expansion (CTE) of the underfill material is larger than that of metal microbumps. This CTE mismatch induces local bending stress in thinned IC chips. This local bending stress would affect CMOS circuit in thinned IC chips. Therefore, we should suppress the local bending stress to realize 3D IC with high reliability. In this work, we propose a novel underfill with negative-CTE filler which can suppress the local bending stress in 3D IC.","PeriodicalId":166245,"journal":{"name":"2016 IEEE International 3D Systems Integration Conference (3DIC)","volume":"72 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133945565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Nano-scale Cu direct bonding using ultra-high density Cu nano-pillar (CNP) for high yield exascale 2.5/3D integration applications 采用超高密度铜纳米柱(CNP)的纳米级铜直接键合，用于高成品率的百亿亿次2.5/3D集成应用
2016 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2016-11-01 DOI: 10.1109/3DIC.2016.7970027
Kang-wook Lee, A. Nakamura, J. Bea, T. Fukushima, S. Ramalingam, Xin Wu, Tanaka Tanaka, M. Koyanagi
{"title":"Nano-scale Cu direct bonding using ultra-high density Cu nano-pillar (CNP) for high yield exascale 2.5/3D integration applications","authors":"Kang-wook Lee, A. Nakamura, J. Bea, T. Fukushima, S. Ramalingam, Xin Wu, Tanaka Tanaka, M. Koyanagi","doi":"10.1109/3DIC.2016.7970027","DOIUrl":"https://doi.org/10.1109/3DIC.2016.7970027","url":null,"abstract":"We propose nano-scale Cu direct bonding technology using ultra-high density Cu nano-pillar (CNP) with for high stacking yield exascale 2.5D/3D integration. We clarified the joining mechanism of nano-scale Cu direct bonding using CNP. Nano-scale Cu pillar easily bond with Cu electrode by re-crystallization of CNP due to the solid phase diffusion and by morphology change of CNP to minimize interfacial energy at relatively lower temperature and pressure compared to conventional micro-scale Cu direct bonding. We confirmed for the first time that 4.3 million electrodes per die are successfully connected in series with the joining yield of 100%. The joining resistance of CNP bundle with 80μm height is around 30 mΩ for each pair of 10μm electrode diameter. Normalized capacitance of CNP bundle with 80μm height is 0.2 fF per μm wire length.","PeriodicalId":166245,"journal":{"name":"2016 IEEE International 3D Systems Integration Conference (3DIC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131156988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design considerations for 2.5-D and 3-D integration accounting for thermal constraints 考虑热约束的2.5-D和3-D集成设计考虑
2016 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2016-11-01 DOI: 10.1109/3DIC.2016.7970032
Yang Zhang, Xuchen Zhang, W. Wahby, M. Bakir
{"title":"Design considerations for 2.5-D and 3-D integration accounting for thermal constraints","authors":"Yang Zhang, Xuchen Zhang, W. Wahby, M. Bakir","doi":"10.1109/3DIC.2016.7970032","DOIUrl":"https://doi.org/10.1109/3DIC.2016.7970032","url":null,"abstract":"In this paper, we explore the design considerations of two approaches to 2.5-D integration (silicon interposer and bridge-chip) from a thermal perspective and compare to 3-D ICs. Moreover, the impact of die thickness mismatch and die spacing are investigated in 2.5-D systems. We conclude that the die dissipating the largest power should be the thickest in a multi-die package. Larger lateral spacing between dice reduces the temperature at the unrealistic expense of communication power efficiency. Therefore, it is necessary to consider this tradeoff when selecting appropriate die spacing.","PeriodicalId":166245,"journal":{"name":"2016 IEEE International 3D Systems Integration Conference (3DIC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126298178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Extreme wafer thinning optimization for via-last applications 通过最后应用的极端晶圆减薄优化
2016 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2016-11-01 DOI: 10.1109/3DIC.2016.7970028
A. Jourdain, J. D. Vos, F. Inoue, K. Rebibis, Andy Miller, G. Beyer, E. Beyne, E. Walsby, Jash Patel, O. Ansell, J. Hopkins, H. Ashraf, D. Thomas
{"title":"Extreme wafer thinning optimization for via-last applications","authors":"A. Jourdain, J. D. Vos, F. Inoue, K. Rebibis, Andy Miller, G. Beyer, E. Beyne, E. Walsby, Jash Patel, O. Ansell, J. Hopkins, H. Ashraf, D. Thomas","doi":"10.1109/3DIC.2016.7970028","DOIUrl":"https://doi.org/10.1109/3DIC.2016.7970028","url":null,"abstract":"As the 3D interconnect density is increasing exponentially when scaling to lower levels of the interconnect wiring, we see that very soon 3D interconnect pitches of 5 μm and below will be required. Current 3D-SIC (3D-Stacked IC) technologies do not yet offer such interconnect densities and it is expected that most of the 3D-SOC (3D System On Chip) integration technology schemes will require a wafer-to-wafer (W2W) bonding approach. The wafer thinning process becomes very critical when final Si thicknesses of the top wafer in the 5μm range or below are considered. Indeed, a good control of the final Si thickness as well as the total thickness variation (TTV) are necessary to enable a stable via-last etch process with minimum undercut (notching). Two extreme wafer thinning approaches are investigated and compared in terms of process performance and cost of ownership.","PeriodicalId":166245,"journal":{"name":"2016 IEEE International 3D Systems Integration Conference (3DIC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124171005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
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