Front-side mid-level Tungsten TSV integration for high-density 3D applications

Abstract

We demonstrate a front-side process integration method to insert high-density 1.2um diameter Tungsten (W) Through Silicon Vias (TSVs) into advanced-node logic wafers after metal-4. This late-TSV-middle approach offers the ability to build 3D technology into commercially available 90nm-node CMOS, while avoiding many of the challenges associated with TSV-last integrations. We also demonstrate a TSV-reveal process compatible with small-diameter W TSVs.