Analog-digital partitioning and coupling in 3D-IC for RF applications

Abstract

This paper presents a part of a cellular transmitter chain implemented in a 28 nm CMOS 3D integrated circuit vertical stack. The design examines various partitioning topolgies between the analog and digital blocks. By using extensive reconfigurability we are able to create a basis for comparison between the partitions as well as between other partitioning solutions as multiple chip, single chip and 2.5D interposer. The design separates the functionality across the die tiers, and utilizes a solenoid inductor for the VCO to obtain higher immunity to coupling. The work demonstrates a significant reduction in the digital link power down to 0.37 pJ/bit and significant attenuation of spurs at the VCO output located above the digital block.