3DIP:用于单片3D集成电路的迭代划分工具

G. Berhault, M. Brocard, S. Thuries, François Galea, Lilia Zaourar
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引用次数: 7

摘要

CoolCubeTM是一种单片3D (M3D)技术,由于采用超薄单片层间过孔(miv),其垂直集成密度比面对面铜混合键合(F2F Cu-Cu)高20倍。在这项工作中,我们提出了一种新的分区工具,利用这一特性,在放置前对2层Cell-on-Cell ic进行分区。它基于一种快速迭代算法,可以探索解决方案的空间,并在不限制miv数量的情况下,在层间平衡面积的情况下最小化电线的估计成本。详细介绍了基于模拟退火(SA)算法和专用代价函数的三维分区问题的数学公式和综合框架,并与常用的最小切割(MC)分区进行了比较。我们的解决方案似乎可以将LDPC和FFT/AES单元的估计总成本分别降低41%和45%。与相同单元的MC算法相比,它还将电线的总成本降低了30%至44%,并且运行时间没有显着增加。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
3DIP: An iterative partitioning tool for monolithic 3D IC
CoolCubeTM is a monolithic 3D (M3D) technology offering a vertical density of integration 20 times higher than face to face copper hybrid bonding (F2F Cu-Cu), thanks to ultra-thin Monolithic Inter-tier Vias (MIVs). In this work, we propose a new partitioning tool exploiting this characteristic for 2-tier Cell-on-Cell ICs before placement. It is based on a fast and iterative algorithm that explores the space of solutions and minimizes the estimated cost of wires with balanced area between tiers without limiting the number of MIVs. A mathematical formulation of the 3D partitioning problem and a comprehensive framework, based on simulated annealing (SA) algorithm coupled with a dedicated cost function, are detailed and compared with Min-Cut (MC) partitions commonly used. It appears that our solution can decrease the estimated total cost of wires by 41% and 45% for the LDPC and FFT/AES units. It also reduces the total cost of wires by 30% to 44% compared to the MC algorithm for the same units and with no significant increase in runtime.
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