Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS)最新文献

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Correlation of lifetimes from CVS and RVS using the 1/E-model for thermally grown oxides on polysilicon 用1/ e模型计算多晶硅上热生长氧化物的CVS和RVS寿命的相关性
Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS) Pub Date : 1994-10-16 DOI: 10.1109/IRWS.1994.515836
A. Martin, P. O'Sullivan, A. Mathewson
{"title":"Correlation of lifetimes from CVS and RVS using the 1/E-model for thermally grown oxides on polysilicon","authors":"A. Martin, P. O'Sullivan, A. Mathewson","doi":"10.1109/IRWS.1994.515836","DOIUrl":"https://doi.org/10.1109/IRWS.1994.515836","url":null,"abstract":"Accelerated stress measurements such as constant voltage stress (CVS) and ramped voltage stress (RVS) are commonly used in industry for the evaluation of oxide lifetimes. The main advantage of RVS over CVS is the short measurement time. Therefore, RVS is widely used, especially, in short dielectric screens and, lifetimes are extrapolated from the RVS measurement results. For this lifetime extrapolation a correlation between RVS data and CVS lifetimes is assumed. This correlation between CVS and RVS results is investigated for six oxides which had been thermally grown from polysilicon. CVS and RVS measurements were performed over a wide range of bias conditions and the measurement results were directly compared. This comparison showed that RVS increases oxide lifetimes. The current-time characteristics were studied in order to find the cause of the increased RVS lifetimes. They indicated lower currents for RVS than for CVS at equal bias voltage levels. Further measurements were carried out to study the effect of a RVS prior to CVS. Findings from these measurements with pre-stressed oxides confirmed the RVS lifetime increase which had been seen earlier. The increase in RVS lifetimes is critical for the prediction of oxide lifetimes at operating voltage. This increase has to be taken into account when lifetimes are predicted from RVS results. If it is not oxide lifetimes will be overestimated.","PeriodicalId":164872,"journal":{"name":"Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129806056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Wafer Level Reliability Utilization and Trends 晶圆级可靠性利用率和趋势
Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS) Pub Date : 1994-10-16 DOI: 10.1109/IRWS.1994.515842
E. Achee
{"title":"Wafer Level Reliability Utilization and Trends","authors":"E. Achee","doi":"10.1109/IRWS.1994.515842","DOIUrl":"https://doi.org/10.1109/IRWS.1994.515842","url":null,"abstract":"This discussion group sought to bring greater understanding of the types and amount of wafer level reliability testing that are used throughout the semiconductor industry. With a greater understanding of what each company is actually practicing in their individual WLR efforts and how these programs have benefited reliability improvements in products, we can change or expand our existing programs uo provide added value. VVe are also looking to highlight the difference between WLR testing that is used as a ongoing monitor and testing that is a true reliability indicator for product. The ultimate goal is to be able to make fact and data based decisions from wafer level testing to prevent us from having to rely on lengthy package level testing results. 'The discussion group was structured to fist identify some of the reasons that we are currently forced to disposition deviate product without the appropriate data. When engineering level data is not available, the decision making process can default to non data based decision making due to issues like economics, time, conjecture, or misuse of data. The second step was to identify the WLR activities and capabilities of the companies represented and the failure mechanism each test monitors or targets. This is a good industry poll of the actual activities in use or final development today and served to show the level of WLR implementation throughout the industry. Slide 2 shows these results. The next step is to identify the actual reliability issues we see today within our industry or companies. These are supposed to be actual failure mechanisms seen today and not mechanisms that monitors are in place to detect. With a comprehensive list of these failure mechanisms, we can identify the existing WLR testing available for the mechanism or identify mechanisms for which we have no current method of testing with current WLR methodologies. Slides 3 & 4 shows the resulting list of failure mechanisms and the WLR tests identified to address these mechanisms. The discussion showed that the companies using particular WLR tests were not necess","PeriodicalId":164872,"journal":{"name":"Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130258154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Degradation of off-state leakage in PMOS transistors under hot carrier injection 热载流子注入下PMOS晶体管失态泄漏的退化
Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS) Pub Date : 1994-10-16 DOI: 10.1109/IRWS.1994.515827
C.H.J. Huang, T. Rost, J. McPherson
{"title":"Degradation of off-state leakage in PMOS transistors under hot carrier injection","authors":"C.H.J. Huang, T. Rost, J. McPherson","doi":"10.1109/IRWS.1994.515827","DOIUrl":"https://doi.org/10.1109/IRWS.1994.515827","url":null,"abstract":"This research investigates the degradation of the off-state leakage current and punchthrough voltage as a function of channel hot carrier stress for buried-channel as well as surface-channel devices. A number of additional parameters such as Idlin, Idsat, Vt, and Gm were also monitored throughout the stress; however, the off-state leakage current degraded the fastest. Changes in leakage current of greater than three orders of magnitude can be hot carrier induced combined with a substantial reduction in punchthrough voltage. Since the off-state leakage has a strong temperature dependence, these effects can become particularly severe at junction temperatures approaching 100/spl deg/C. The activation energy of the hot carrier temperature dependence was calculated to be about -0.2 eV. Degradation rate modeling indicated a simple power law dependence on maximum gate current with an exponent of 2. It was shown that hot carrier robustness could be improved in pMOS transistors by implementing an LDD structure.","PeriodicalId":164872,"journal":{"name":"Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114834261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A new index for gate oxide reliability characterization 一种新的栅极氧化物可靠性表征指标
Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS) Pub Date : 1994-10-16 DOI: 10.1109/IRWS.1994.515838
B. Lisenker
{"title":"A new index for gate oxide reliability characterization","authors":"B. Lisenker","doi":"10.1109/IRWS.1994.515838","DOIUrl":"https://doi.org/10.1109/IRWS.1994.515838","url":null,"abstract":"A new integral index (K-factor) for gate oxide (GOX) quality and reliability prediction is introduced. The physical meaning of this factor is that a charge leaking through a unit of volume of dielectric, induces a unit change in built-in electric field. The theoretical and experimental background together with examples of the K-factor application for comparing and characterization various gate oxides are presented and discussed. The advantages of this new technique, that should replace the QBD test, are demonstrated.","PeriodicalId":164872,"journal":{"name":"Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121741793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Whole-chip ESD protection for CMOS VLSI/ULSI with multiple power pins 多电源引脚CMOS VLSI/ULSI的全片ESD保护
Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS) Pub Date : 1994-10-16 DOI: 10.1109/IRWS.1994.515839
M. Ker, Chung-Yu Wu, Tao Cheng, M.J.-N. Wu, Talee Yu, A.C. Wang
{"title":"Whole-chip ESD protection for CMOS VLSI/ULSI with multiple power pins","authors":"M. Ker, Chung-Yu Wu, Tao Cheng, M.J.-N. Wu, Talee Yu, A.C. Wang","doi":"10.1109/IRWS.1994.515839","DOIUrl":"https://doi.org/10.1109/IRWS.1994.515839","url":null,"abstract":"An anomalous phenomenon of ESD failure in CMOS ICs with multiple VDD and VSS power-supply pins is discovered and investigated. A method of whole-chip ESD protection to overcome this anomalous ESD failure is proposed with experimental verification.","PeriodicalId":164872,"journal":{"name":"Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121825454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Evaluation of self-heating in SOI CMOS ULSI SOI CMOS ULSI中自热特性的评价
Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS) Pub Date : 1994-10-16 DOI: 10.1109/IRWS.1994.515832
D. Dallmann, K. Shenai
{"title":"Evaluation of self-heating in SOI CMOS ULSI","authors":"D. Dallmann, K. Shenai","doi":"10.1109/IRWS.1994.515832","DOIUrl":"https://doi.org/10.1109/IRWS.1994.515832","url":null,"abstract":"SOI technology potentially offers numerous benefits over bulk silicon at deep submicron dimensions. However, the presence of a buried SiO/sub 2/ layer causes self-heating to occur which can impair device performance. The effects of self-heating on SOI MOSFET performance are examined as device dimensions are scaled from 1.0 /spl mu/m to 0.25 /spl mu/m. Results show severe self-heating under static conditions which has implications for IC reliability issues.","PeriodicalId":164872,"journal":{"name":"Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129540157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Evaluation of the predictive capability of Berkeley's hot-carrier reliability model 伯克利热载波可靠性模型的预测能力评估
Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS) Pub Date : 1994-10-16 DOI: 10.1109/IRWS.1994.515848
A. Meehan, P. O'Sullivan, P. Hurley, A. Mathewson
{"title":"Evaluation of the predictive capability of Berkeley's hot-carrier reliability model","authors":"A. Meehan, P. O'Sullivan, P. Hurley, A. Mathewson","doi":"10.1109/IRWS.1994.515848","DOIUrl":"https://doi.org/10.1109/IRWS.1994.515848","url":null,"abstract":"A model for hot-carrier reliability prediction developed at the University of California is widely used in industry. Confusion exists, however, as to how the model is to be applied. The model's devisers suggest that hot-carrier degradation is most rapid when substrate current is maximum, yet the model itself is in strong disagreement with this. Since the minimum lifetime for a given drain voltage is of most interest, the minimum prediction of the model needs to be evaluated. The necessity of using a novel hot-carrier stress method in the evaluation is demonstrated.","PeriodicalId":164872,"journal":{"name":"Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129062932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Self-stressing structures for wafer-level oxide breakdown to 200 MHz 用于晶圆级氧化物击穿至200 MHz的自应力结构
Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS) Pub Date : 1994-10-16 DOI: 10.1109/IRWS.1994.515837
E. Snyder, D. Tanner, M.R. Bowles, S. Swanson, C. Anderson, J. P. Perry
{"title":"Self-stressing structures for wafer-level oxide breakdown to 200 MHz","authors":"E. Snyder, D. Tanner, M.R. Bowles, S. Swanson, C. Anderson, J. P. Perry","doi":"10.1109/IRWS.1994.515837","DOIUrl":"https://doi.org/10.1109/IRWS.1994.515837","url":null,"abstract":"We have demonstrated for the first time high frequency (210 MHz) oxide breakdown at the wafer-level using on-chip, self-stressing test structures. This is the highest frequency oxide breakdown that has been reported. We used these structures to characterize the variation in oxide breakdown with frequency (from 1 Hz to over 200 MHz) and duty cycle (from 10% to 90%). Since the stress frequency, duty cycle and temperature are controlled by DC signals in these structures, we used conventional DC wafer-level equipment without any special modifications (such as high frequency cabling). This self-stressing structure significantly reduces the cost of performing realistic high frequency oxide breakdown experiments necessary for developing reliability models and building-in-reliability.","PeriodicalId":164872,"journal":{"name":"Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124244524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Antifuse reliability and link formation models 抗熔断可靠性和链路形成模型
Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS) Pub Date : 1994-10-16 DOI: 10.1109/IRWS.1994.515833
A. Iranmanesh, Y. Karpovich, Sukyoon Yoon
{"title":"Antifuse reliability and link formation models","authors":"A. Iranmanesh, Y. Karpovich, Sukyoon Yoon","doi":"10.1109/IRWS.1994.515833","DOIUrl":"https://doi.org/10.1109/IRWS.1994.515833","url":null,"abstract":"Antifuse devices have been used for a variety of programmable circuits, and their application for high-performance, high density FPGA products is dramatically increasing. Attractiveness of antifuse stems from its relative small size, low ON resistance, and low OFF capacitance. Even though antifuses are conceptually simple structures, their behavior is not well understood. This report attempt to shed light into the link formation and reliability of antifuses. According to the models presented, link formation during programming is caused by melting and solidification of a-Si and portions of the electrodes. Furthermore, link switch-off failure is shown to occur at fixed voltage range caused by link melting. These models can be extended to the other types of antifuses as well.","PeriodicalId":164872,"journal":{"name":"Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129895619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
BUILDING-IN RELIABILITY DISCUSSION GROUP: CUSTOMER/SUPPLIER RELATIONSHIPS 建立可靠性讨论小组:客户/供应商关系
Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS) Pub Date : 1994-10-16 DOI: 10.1109/IRWS.1994.515840
W. K. Gladden
{"title":"BUILDING-IN RELIABILITY DISCUSSION GROUP: CUSTOMER/SUPPLIER RELATIONSHIPS","authors":"W. K. Gladden","doi":"10.1109/IRWS.1994.515840","DOIUrl":"https://doi.org/10.1109/IRWS.1994.515840","url":null,"abstract":"At the 1993 Workshop, Bob Thomas hghlighted the changes in customer viewpoint he: believed were necessary in moving to BIR. Although he focused on customers, he did note two critical issues for us as reliability engineers: 1) BIR means developing strategic partnerships, and 2) An educated customer makes the best partner. With these ideas in mind, the aim of the goup discussions was to consider the tension in viewpoints that develops between customers and suppliers and determine how we as suppliers manage that tension..","PeriodicalId":164872,"journal":{"name":"Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129975962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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