Degradation of off-state leakage in PMOS transistors under hot carrier injection

This research investigates the degradation of the off-state leakage current and punchthrough voltage as a function of channel hot carrier stress for buried-channel as well as surface-channel devices. A number of additional parameters such as Idlin, Idsat, Vt, and Gm were also monitored throughout the stress; however, the off-state leakage current degraded the fastest. Changes in leakage current of greater than three orders of magnitude can be hot carrier induced combined with a substantial reduction in punchthrough voltage. Since the off-state leakage has a strong temperature dependence, these effects can become particularly severe at junction temperatures approaching 100/spl deg/C. The activation energy of the hot carrier temperature dependence was calculated to be about -0.2 eV. Degradation rate modeling indicated a simple power law dependence on maximum gate current with an exponent of 2. It was shown that hot carrier robustness could be improved in pMOS transistors by implementing an LDD structure.