{"title":"Case study: MOSFET instability due to charging of remnant stringers from a disposable polysilicon spacer process","authors":"J. Miller, H.L. Hegedus, V. Kaushik","doi":"10.1109/IRWS.1994.515845","DOIUrl":"https://doi.org/10.1109/IRWS.1994.515845","url":null,"abstract":"Incompletely etched polysilicon \"stringers\" can produce a wide range of failure mechanisms in advanced integrated circuits. Parasitic leakage paths are often the direct cause of failures, but stringers can also form unwanted implant masks, or even act as the conducting channels of parasitic thin film transistors. A failure analysis case study was presented in which remnant stringers from a disposable polysilicon LDD spacer process led to large scale product fallout during burn-in. As a first step in the investigation, a series of circuit and transistor level stress experiments were performed. These produced evidence of significant transistor instability as the likely failure mechanism. Next a detailed Cross-section Transmission Electron Microscopy (XTEM) analysis was performed in order to relate the microstructure of the transistors to the observed electrical performance. The XTEM images clearly showed very small (30-70 nm) remnant polysilicon stringers at the edge of the gate poly reoxidation, above the transistor source/drain regions. The stringers were attributed to incomplete removal of the sidewall spacer polysilicon. This was confirmed by XTEM images of devices pulled from the fab before spacer etch. Finally, additional transistor electrical tests were performed to prove that these stringers acted as parasitic floating gates, gradually charging under saturation bias conditions. It was shown that this trapped charge, located just above the drain region, had a profound effect on subsequent device operation.","PeriodicalId":164872,"journal":{"name":"Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124901957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Improved electromigration test techniques of layered metal structures at wafer level","authors":"H. Katto","doi":"10.1109/IRWS.1994.515849","DOIUrl":"https://doi.org/10.1109/IRWS.1994.515849","url":null,"abstract":"The current constant stress (J-constant) technique is useful for evaluating the resistance rise, but can not evaluate \"n\" values because of metal temperature scattering among samples. Two modified Jc techniques are advised. By controlling the metal temperature at t(stress)=0 within /spl plusmn/1/spl deg/C of the target temperature, the \"temperature-controlled\" J-constant technique can evaluate n values efficiently. By monitoring the power and adjusting the stress current, the power-constant technique can reduce excess joule-heating and keep the metal temperature constant during stress, and smaller n values are obtained.","PeriodicalId":164872,"journal":{"name":"Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115563653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Circuit-level electrothermal simulation techniques for designing output protection devices","authors":"S. Ramaswamy, E. Rosenbaum, S. Kang","doi":"10.1109/IRWS.1994.515831","DOIUrl":"https://doi.org/10.1109/IRWS.1994.515831","url":null,"abstract":"The design of I/O protection circuits is crucial for the reliable operation of integrated circuits. Typical protection circuits are designed to meet certain specifications (ESD/EOS failure levels) and the use of CAD tools in the design stage will help in their characterization and design. We recently developed a circuit-level electrothermal simulator, iETSIM, which we have used to study different protection circuit designs. iETSIM solves the heat diffusion equation simultaneously with the device electrical equations. The device models extend to the avalanche breakdown regime. We show that the circuit-level electrothermal simulator can be a useful tool for designing reliable output protection devices.","PeriodicalId":164872,"journal":{"name":"Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130567759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A model of temperature cycling performance in plastic encapsulated packages","authors":"P. Syndergaard, J. Young","doi":"10.1109/IRWS.1994.515824","DOIUrl":"https://doi.org/10.1109/IRWS.1994.515824","url":null,"abstract":"A requirement for many customers of semiconductors encapsulated in plastic packages is the ability to survive 1000 cycles of air-to-air (gas-to-gas) temperature cycle under the conditions of -65/spl deg/C to +150/spl deg/C. A series of experiments were performed to model the performance of molding compounds relative to die size. The model was then correlated to the historical temperature cycling data of an encapsulant independent of package size or type. The temperature cycle performance can now be predicted based on die size. The package size or type is incidental, a larger package is generally required for a larger die.","PeriodicalId":164872,"journal":{"name":"Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121824692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The practical side of thin dielectric monitoring and characterization","authors":"J. Suehle, C. Messick, B. Langley","doi":"10.1109/IRWS.1994.515818","DOIUrl":"https://doi.org/10.1109/IRWS.1994.515818","url":null,"abstract":"The proper characterization and monitoring of gate dielectric reliability become critical functions in IC manufacturing and development as gate oxide thickness is scaled. Reliability engineers are faced with decisions concerning the test to use, the parameters of the test, test structure design, equipment, data analysis, and extrapolation to use conditions. This tutorial addresses many of these issues by providing examples of test structures, testing techniques, data analysis, and experimental case histories regarding long-term time-dependent dielectric breakdown (TDDB) testing, monitoring dielectric integrity via highly accelerated ramp tests, and characterizing plasma-induced damage.","PeriodicalId":164872,"journal":{"name":"Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129901330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Assembly test chips and circuits for detecting and measuring mechanical damage in packaged ICs","authors":"J. Sweet","doi":"10.1109/IRWS.1994.515823","DOIUrl":"https://doi.org/10.1109/IRWS.1994.515823","url":null,"abstract":"Die cracking and stress induced damage to metal conductors in plastic package integrated circuits have become major reliability issues in recent times. Test chips with structures which can detect cracking or metal damage can be used to qualify new types of packaging. The Sandia stress sensing chip, ATC04, can make quantitative measurements of in-plane shearing stress which can in turn be related to the shearing stresses which produce metal motion. Recent stress measurements with liquid encapsulated ATC04 parts are reviewed and accuracy limits discussed. Other types of test chips attempt to detect thin film cracking or delamination by electrical detection of damage to conductor structures in or near chip corners. Several designs of such chips are discussed.","PeriodicalId":164872,"journal":{"name":"Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130395446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Dion, J. Hackenberg, D. Hemmenway, L.G. Pearce, J. W. Werner
{"title":"Investigation of plasma process damage in a thick gate oxide, large geometry, process using protected devices","authors":"M. Dion, J. Hackenberg, D. Hemmenway, L.G. Pearce, J. W. Werner","doi":"10.1109/IRWS.1994.515826","DOIUrl":"https://doi.org/10.1109/IRWS.1994.515826","url":null,"abstract":"Plasma process induced damage is a major device issue. A non-uniform plasma can generate significant MOS gate damage and this damage is commonly reported on state-of-the-art thin oxides and small devices. This work will describe plasma damage observed on a thick gate, large geometry process. Protected devices were used to confirm plasma damage. Protected devices for study of damage along with issues with fuse protection are discussed. Blowing of fuses may be better than laser cutting and fuse protection of all device nodes may not be needed.","PeriodicalId":164872,"journal":{"name":"Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS)","volume":"47 Pt B 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133036046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Standardization of wafer level reliability techniques-JEDEC 14.2","authors":"M. Dion","doi":"10.1109/IRWS.1994.515847","DOIUrl":"https://doi.org/10.1109/IRWS.1994.515847","url":null,"abstract":"Summary form only given. JEDEC stands for: Joint Electronic Device Engineering Council and is sometimes known as simply \"The Council\", and is the engineering standardization body ofthe Electronic Industry Association (EIA). Promoting development and standardization of test methods, nomenclature and product characterization are primary functions of the Council. The Council establishes Committees to conduct its standardization activities, with the primary function of each Committee being to propose standards, procedures, etc., and submit them to the Council for action or approval. Reliability is handled by JEDEC Committee 14 (JC 14) \"Committee on Quality and Reliability of Solid State Products\". As its title implies JC 14 is responsible for generation and maintenance of quality and reliability standards for solid state products. Currently there are seven active JC 14 subcommittees, one of which is JC 14.2, whose scope includes generation of terms, definitions and establishment and/or review of specifications and standards relating to wafer level assessment of semiconductor devices. This committee also provides a forum for discussion of wafer level reliability assessment of all types. Most methods, techniques and standards developed for wafer level assessment work equally well with packaged devices.","PeriodicalId":164872,"journal":{"name":"Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126876601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Enhanced degradation of nMOSFET's under hot carrier stress at elevated temperatures due to the length of velocity saturation region","authors":"H. Hwang, J. Goo, H. Kwon, Hyungsoon Shin","doi":"10.1109/IRWS.1994.515829","DOIUrl":"https://doi.org/10.1109/IRWS.1994.515829","url":null,"abstract":"The anomalous behavior of nMOSFET's hot carrier reliability characteristics have been investigated at an elevated temperature. We found that degradations of saturation drain current and ring oscillator falling time are enhanced at high temperature. This anomalous behavior causes a significantly impact on the device reliability for future deep submicron devices at high operating temperatures.","PeriodicalId":164872,"journal":{"name":"Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124131154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Discussion Group Summary Report Qualification Elimination","authors":"D. L. Erhart","doi":"10.1109/IRWS.1994.515841","DOIUrl":"https://doi.org/10.1109/IRWS.1994.515841","url":null,"abstract":"This discussion group was directed toward the possibility of eliminating the traditional product qualification. The basic objective of this discussion group was to explore the issues or preconceptions that were limiting us to the traditional qualification approach. The mechanics of the two discussion group sessions were fairly straightforward. I had prepared several overhead transparencies that were meant to provide a basis for exploring our existing qualification and reliability risk management process. I started my presentation with an overview of the origins of our current methodology. As questions arose or as comments or clarifications were offered by session attendees, we stopped the formal presentation and explored the issue or question further. If no further discussion ensued, I returned to my prepared slides. We proceeded in this way until our time ran out. The level of participation by session attendees was very high in both sessions. The backgrounds and interests of the attendees in the two sessions were quite different. As a result, the issues discussed, and the discussion points that were emphasized in the two sessions were generally different. In the following paragraphs I will attempt to capture the key points from both sessions. A predominant theme from both sessions was that the customer-supplier relationship would determine the likelihood of shifting from the traditional qualification methodology to any alternative procedure. It was suggested that vertically integrated companies may have an advantage since they operate on both sides of the customersupplier relationship. Representatives from a few vertically integrated companies seemed to support this belief. In the absence of an internal customer-supplier relationship, several people mentioned that they were cultivating very close partnerships with their key customers. They commented that there was a lack of trust between suppliers and customers. Specific instances where suppliers selectively shared qualification results with customers were offered by customer and supplier representatives in the session. The suppliers claimed that in some situations the sophistication of the customer might dictate the level of openness that a supplier would offer to a customer. In their assessment, the more sophisticated the customer was, the more the details (in this case the details are possible qualification failures or concerns about new failure modes) of the reliability assessment could be shared. Unsophisticated customers were generally thought to be incapable of dealing with the details, and tended to be more dogmatic in their qualification requirements. Although the reasons for this mistrust were varied, there was general agreement that without a higher degree of trust, primarily on the part of customers, any attempt to unilaterally change the rules of the “Qualification Game” would fail. A key discussion topic was how to implement anything other than the historical qualification. The con","PeriodicalId":164872,"journal":{"name":"Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133216394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}