Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS)最新文献_第3页

Production implementation of a practical WLR program 生产实现了一个实用的WLR程序

Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS) Pub Date : 1994-10-16 DOI: 10.1109/IRWS.1994.515822

S. Garrard

{"title":"Production implementation of a practical WLR program","authors":"S. Garrard","doi":"10.1109/IRWS.1994.515822","DOIUrl":"https://doi.org/10.1109/IRWS.1994.515822","url":null,"abstract":"Wafer Level Reliability (WLR) programs have been active in many semiconductor companies since the early 1980s. Test structures are designed to accelerate known reliability failure mechanisms. Large samples of these test structures are packaged and tested to determine reliability failure rates. These WLR programs typically focus on electromigration (EM), hot carrier, and TDDB testing of packaged parts. National Semiconductor has developed and implemented a WLR program which differs from the traditional approach. Wafer manufacturing personnel need to know which people, equipment, or process variables need to be better controlled to prevent reliability problems in the field. They also need faster feedback, Our WLR program looked at these issues and a more practical approach to eliminating fab-related reliability problems. Wafers, not packaged parts, are tested in-line and at the end of line (before sort test) to provide near-real-time feedback. We identified our top ten reliability failure mechanisms of concern based on past field failure rates and reliability monitors. WLR test structures and test methods were then designed to measure the effect of wafer fab process variability on reliability risk. Designed experiments were used extensively to correlate fab process monitors, WLR test results, and reliability test results.","PeriodicalId":164872,"journal":{"name":"Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133875824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Reliability Modeling and Simulation Discussion Group 可靠性建模与仿真讨论组

Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS) Pub Date : 1994-10-16 DOI: 10.1109/IRWS.1994.515843

E. Rosenbaum, K. Shenai

引用次数: 0

Enhanced EM endurance of TiN/AlCu/TiN/sub x/ interconnection TiN/AlCu/TiN/sub / x/互连的耐EM能力增强

Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS) Pub Date : 1994-10-16 DOI: 10.1109/IRWS.1994.515844

J. Byun, J. K. Kim, K. Rha, W. Kim

{"title":"Enhanced EM endurance of TiN/AlCu/TiN/sub x/ interconnection","authors":"J. Byun, J. K. Kim, K. Rha, W. Kim","doi":"10.1109/IRWS.1994.515844","DOIUrl":"https://doi.org/10.1109/IRWS.1994.515844","url":null,"abstract":"Summary form only given. In submicron devices, TiN is used as a barrier layer in multilayered aluminum interconnection (e.g., TiN/Al/TiN). The conventional TiN layer is formed by reactive sputtering, which shows a columnar grain structure about the size of 10 nm. In this study, we focused on another technique of forming TiN from TiN/sub x/, and compared the electromigration (EM) endurance of the multilayered interconnections using TiN/sub x/ and conventional TiN. In order to investigate the structural aspects of aluminum and the TiN formed from the TiN/sub x/ layer, the samples were prepared as follows. TiN/sub x/ film of 50 nm thickness was reactively deposited on the oxidized (400 nm thick) silicon wafer by using DC magnetron sputtering in a mixed gas atmosphere of argon and nitrogen, in which the volume percent of nitrogen was fixed at 15%. After thermal treatment at 600 /spl deg/C for 20 sec using RTA, Al-0.5%Cu film (500 nm thick) and TiN (40 nm thick) film were sequentially deposited. After patterning of aluminum stripes of 0.4 /spl mu/m width and 1400 /spl mu/m length, the samples were alloyed at 400 /spl deg/C, 30 min in 15% H/sub 2//N/sub 2/ ambient. Finally, a passivation layer consisting of CVD nitride (1.2 /spl mu/m thick) and CVD oxide (0.4 /spl mu/m thick) was deposited. The film properties before and after RTA were analyzed using RBS, XRD, and AES. Such an interconnection showed extremely high EM endurance (MTTF /spl sim/ 10/sup 4/ min) in comparison with that using the conventional TiN as an underlying barrier layer (MTTF /spl sim/10/sup 2/ min). It is suggested that the crystal continuity between the Al and the TiN suppresses interface and grain boundary diffusion of Al atoms to improve the EM endurance.","PeriodicalId":164872,"journal":{"name":"Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115261450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Gate oxide reliability: the use of simulation to quantify important aspects of lifetime projection from TDDB data 栅极氧化物可靠性:使用模拟来量化TDDB数据的寿命预测的重要方面

Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS) Pub Date : 1994-10-16 DOI: 10.1109/IRWS.1994.515834

W. Hunter

引用次数: 10

An electrical method for determining the thickness of metal films and the cross-sectional area of metal lines 测定金属膜厚度和金属线截面积的电学方法

Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS) Pub Date : 1994-10-16 DOI: 10.1109/IRWS.1994.515820

H. Schafft, S. Mayo, S. Jones, J. Suehle

引用次数: 3

Call to Participate in Second Interlaboratory Electromigration Experiment 第二次实验室间电迁移实验征集

Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS) Pub Date : 1994-10-16 DOI: 10.1109/IRWS.1994.515850

H. Schafft, E. Achee

{"title":"Call to Participate in Second Interlaboratory Electromigration Experiment","authors":"H. Schafft, E. Achee","doi":"10.1109/IRWS.1994.515850","DOIUrl":"https://doi.org/10.1109/IRWS.1994.515850","url":null,"abstract":"The first interlaboratory experiment was conducted by NIST in the middle eighties to assess the industry's measurement capability, using their own test methods, for measuring electromigration t,, and sigma, and to identify sources for variability. This effort resulted from recommendations that were made to NIST at the 1983 Wafer Level Reliability Workshop. The results of that experiment were published [l] and used in the preparation of an ASTM standard method, ASTM F1260 121. The method now requires a determination of the interlaboratory precision of the method -otherwise it will soon be discontinued as an ASTM standard. Plans are underway to conduct a second interlaboratory experiment, where the participating laboratories will use the standard method to make their measurements. The purposes of the experiment are to determine the precision of the method, re-evaluate the sources for variability, refine the standard, and permit calibration with the reference laboratory, NIST. In preparation, a NIST test station for packagelevel testing has been assembled and new test and analysis software has been written in a collaborative effort with NIST guest researcher E.T. AchCe, of AMD. Ehren T. Achke AMD Austin, TX Tel: 512-602-5657 ehren.achee@amd.com","PeriodicalId":164872,"journal":{"name":"Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127616130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Circuit hot carrier reliability simulation in advanced CMOS process technology development 电路热载流子可靠性仿真在先进CMOS工艺技术发展中的应用

Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS) Pub Date : 1994-10-16 DOI: 10.1109/IRWS.1994.515830

P. Fang, P.C. Li, J. Yue

引用次数: 2

JEDEC "TCR" interlaboratory experiment-lessons learned JEDEC“TCR”实验室间实验经验教训

Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS) Pub Date : 1994-10-16 DOI: 10.1109/IRWS.1994.515821

H. Schafft, J. Suehle, J. Albers

引用次数: 1

Practical application of a wafer level reliability qualification 晶圆级可靠性鉴定的实际应用

Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS) Pub Date : 1994-10-16 DOI: 10.1109/IRWS.1994.515846

J. May, H. Hoang

{"title":"Practical application of a wafer level reliability qualification","authors":"J. May, H. Hoang","doi":"10.1109/IRWS.1994.515846","DOIUrl":"https://doi.org/10.1109/IRWS.1994.515846","url":null,"abstract":"Deficiencies in the traditional approach to ensuring product reliability (e.g. package level testing) were first noted way back in the early 1970's. However, it was not until the late 1980's to early 1990's that WLRC was seriously considered and began to be implemented across the industry. This new approach for achieving greater levels of reliability required a fundamental change from the mind set of reliability verification on finished products (screening the outputs) to comprehending and controlling the various factors that determine reliability (controlling the inputs). This mind set is known as \"building-in\" or \"designing-in\" reliability and envisions a total reliability assurance and improvement strategy that is executed at all stages of semiconductor manufacturing. To meet the challenge of continuous improvement, it is now a corporate policy that a WLRC program be required at all R&D and production facilities with the intention of determining and eliminating all faults at their source of origin. Emphasis is placed on the use of wafer level reliability testing for introducing and qualifying new semiconductor technology and controlling production once technology has been transferred to the wafer fab. The description, philosophy and issues of integrating the WLRC program into a manufacturing environment have been described previously. Here a practical application is presented. As an example, the development, execution and results of a WLR qualification and production control plan for an advanced, submicron, triple-level metal CMOS process is provided.","PeriodicalId":164872,"journal":{"name":"Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133919502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Mobile ion contamination in CMOS circuits: a clear and present danger CMOS电路中的移动离子污染:一个明确而现实的危险

Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS) Pub Date : 1994-10-16 DOI: 10.1109/IRWS.1994.515819

Roberl, Hance, Kent Erington

引用次数: 6