多电源引脚CMOS VLSI/ULSI的全片ESD保护

Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS) Pub Date : 1994-10-16 DOI:10.1109/IRWS.1994.515839

M. Ker, Chung-Yu Wu, Tao Cheng, M.J.-N. Wu, Talee Yu, A.C. Wang

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引用次数: 13

摘要

本文发现并研究了具有多个VDD和VSS电源引脚的CMOS集成电路中ESD失效的异常现象。提出了一种克服这种异常ESD失效的全芯片ESD保护方法，并进行了实验验证。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Whole-chip ESD protection for CMOS VLSI/ULSI with multiple power pins

An anomalous phenomenon of ESD failure in CMOS ICs with multiple VDD and VSS power-supply pins is discovered and investigated. A method of whole-chip ESD protection to overcome this anomalous ESD failure is proposed with experimental verification.

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Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS)

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