24th Annual Technical Digest Gallium Arsenide Integrated Circuit (GaAs IC) Symposiu最新文献

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44 GHz fully integrated and differential monolithic VCOs with wide tuning range in AlInAs/InGaAs/InP DHBT 44 GHz全集成和差分单片vco,具有宽调谐范围的AlInAs/InGaAs/InP DHBT
A. Kurdoghlian, M. Mokhtari, C. Fields, S. Thomas
{"title":"44 GHz fully integrated and differential monolithic VCOs with wide tuning range in AlInAs/InGaAs/InP DHBT","authors":"A. Kurdoghlian, M. Mokhtari, C. Fields, S. Thomas","doi":"10.1109/GAAS.2002.1049079","DOIUrl":"https://doi.org/10.1109/GAAS.2002.1049079","url":null,"abstract":"A fully integrated and differential AlInAs/InGaAs/InP DHBT voltage controlled oscillator (VCO) with wide tuning range and integrated divide-by-2 static divider was demonstrated for 44 GHz wireless and optical communication applications. To our knowledge, these 44 GHz ICs are the highest frequency fundamental mode fully integrated and differential VCOs with wide tuning range ever reported. The 44 GHz fundamental VCO delivers a typical differential output power of +4 dBm at a center frequency of 44 GHz with a tuning range of up to 4.5 GHz. The measured phase noise shows better than -100 dBc/Hz at 1 MHz offset and better than -80 dBc/Hz at 100 kHz offset. We have achieved more than 6 dB improvement in phase noise performance over the differential SHBT VCO results that we reported last year (A. Kurdoghlian et al., IEEE GaAs IC Symp. Dig., pp. 129-132, 2001).","PeriodicalId":142875,"journal":{"name":"24th Annual Technical Digest Gallium Arsenide Integrated Circuit (GaAs IC) Symposiu","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126262333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Adaptive modeling and design of highly integrated 3D microwave-millimeter wave radio front-ends 高集成三维微波毫米波射频前端的自适应建模与设计
E. Tentzeris
{"title":"Adaptive modeling and design of highly integrated 3D microwave-millimeter wave radio front-ends","authors":"E. Tentzeris","doi":"10.1109/GAAS.2002.1049040","DOIUrl":"https://doi.org/10.1109/GAAS.2002.1049040","url":null,"abstract":"The FDTD and the Haar-based MRTD algorithms are applied to the full-wave modeling of highly integrated 3D microwave and millimeter wave radio front-ends that require the optimization of various components as well as the minimization of the crosstalk between them. The numerical results have demonstrated a very good computational efficiency in the calculation of the scattering parameters, the Q-factor, as well as in the estimation of the radiation pattern, of the packaging effects and of the parasitic crosstalk between neighboring geometries.","PeriodicalId":142875,"journal":{"name":"24th Annual Technical Digest Gallium Arsenide Integrated Circuit (GaAs IC) Symposiu","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126400358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
InP/GaAsSb/InP double heterojunction bipolar transistors InP/GaAsSb/InP双异质结双极晶体管
C. Bolognesi, M. Dvorak, S. Watkins
{"title":"InP/GaAsSb/InP double heterojunction bipolar transistors","authors":"C. Bolognesi, M. Dvorak, S. Watkins","doi":"10.1109/GAAS.2002.1049074","DOIUrl":"https://doi.org/10.1109/GAAS.2002.1049074","url":null,"abstract":"InP/GaAsSb/InP double heterojunction bipolar transistors (DHBTs) are some of the fastest bipolar transistors ever fabricated, with current gain cutoff and maximum oscillation frequencies simultaneously exceeding 300 GHz while maintaining breakdown voltages BV/sub CEO/ > 6 V. InP/GaAsSb/InP DHBTs are particularly appealing because excellent device figures of merit are achievable with relatively simple structures involving abrupt junctions and uniform doping levels and compositions: this is a tremendous manufacturability advantage in comparison to GaInAs-based alternatives. This paper highlights some important physical aspects of the use of GaAsSb base layers. In particular, we describe the implications of the staggered band line-up at the E/B and B/C heterojunctions for charge storage in the devices, and show that InP/GaAsSb/InP DHBTs offer inherent advantages with direct implications to applications in high-speed digital circuits.","PeriodicalId":142875,"journal":{"name":"24th Annual Technical Digest Gallium Arsenide Integrated Circuit (GaAs IC) Symposiu","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133809305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 40 Gb/s integrated differential PIN+TIA with DC offset control using InP SHBT technology 40gb /s集成差分PIN+TIA,采用InP SHBT技术进行直流偏置控制
D. Caruth, S. Shen, D. Chan, M. Feng, J. Schutt-Ainé
{"title":"A 40 Gb/s integrated differential PIN+TIA with DC offset control using InP SHBT technology","authors":"D. Caruth, S. Shen, D. Chan, M. Feng, J. Schutt-Ainé","doi":"10.1109/GAAS.2002.1049029","DOIUrl":"https://doi.org/10.1109/GAAS.2002.1049029","url":null,"abstract":"Describes the design and measured performance of a 40 Gb/s integrated differential PIN+TIA with offset control using InP SHBT technology. The circuit was designed to handle large average optical input power levels (>5 dBm) encountered in short-haul networks where optical gain control may not be available or economical.","PeriodicalId":142875,"journal":{"name":"24th Annual Technical Digest Gallium Arsenide Integrated Circuit (GaAs IC) Symposiu","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132748737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A 2.4 & 5 GHz dual band 802.11 WLAN supporting data rates to 108 Mb/s 2.4和5 GHz双频802.11 WLAN支持数据速率为108 Mb/s
B. McFarland, A. Shor, A. Tabatabaei
{"title":"A 2.4 & 5 GHz dual band 802.11 WLAN supporting data rates to 108 Mb/s","authors":"B. McFarland, A. Shor, A. Tabatabaei","doi":"10.1109/GAAS.2002.1049018","DOIUrl":"https://doi.org/10.1109/GAAS.2002.1049018","url":null,"abstract":"A three chip set, and its associated reference design, implementing a dual mode, dual band 802.11 a/b WLAN is presented. The reference design achieves -91 dBm sensitivity at 6 Mb/s, -73 dBm at 54 Mb/s, and -70 dBm at 108 Mb/s. 18 dBm transmit power is achieved at 6 Mb/s, 14 dBm at 54 and 108 Mb/s. An overview of 802.11a is given. Worldwide spectral allocations are summarized. Required RF component performance is described including PA linearity and achievable PA efficiencies.","PeriodicalId":142875,"journal":{"name":"24th Annual Technical Digest Gallium Arsenide Integrated Circuit (GaAs IC) Symposiu","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131891710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
High-performance and high-uniformity InP/InGaAs/InP DHBT technology for high-speed optical communication systems 用于高速光通信系统的高性能和高均匀性InP/InGaAs/InP DHBT技术
Y. Yang, J. Frackoviak, C. Liu, C.J. Chen, L. Chua, W. Sung, A. Tate, J. Tong, R. Reyes, R. Kopf, R. Ruel, D. Werder, V. Houtsma, G. Georgiou, J. Weiner, Y. Baeyens, Y. Chen
{"title":"High-performance and high-uniformity InP/InGaAs/InP DHBT technology for high-speed optical communication systems","authors":"Y. Yang, J. Frackoviak, C. Liu, C.J. Chen, L. Chua, W. Sung, A. Tate, J. Tong, R. Reyes, R. Kopf, R. Ruel, D. Werder, V. Houtsma, G. Georgiou, J. Weiner, Y. Baeyens, Y. Chen","doi":"10.1109/GAAS.2002.1049075","DOIUrl":"https://doi.org/10.1109/GAAS.2002.1049075","url":null,"abstract":"Recently, InP/InGaAs/InP double-heterostructure bipolar transistors (DHBT) have attracted a lot of attention in the realization of high-speed (>40 Gb/s) optical communication systems (G. Raghaven et al., IEEE Spectrum, Oct. 2000; Y. Baeyens et al, IEEE GaAs IC Symp. Tech. Dig., pp. 125-128, 2001; Y.K. Chen et al., IEDM Tech. Dig., 2001, and OFC Tech. Dig., 2002). Much progress has been made to improve the high-speed device performance and f/sub T/ values as high as 340 GHz have been reported (S. Lee et al, IEEE GaAs IC Symp. Tech. Dig., pp. 185-187, 2001; A. Fujihara et al., IEDM Tech. Dig., 2001; M. Ida et al., ibid., 2001.). However to our knowledge there have been few reports on the reproducibility, yield and robustness of these types of devices. For successful implementation of these devices in high speed ICs, in addition to high f/sub T/ and f/sub max/, a useful DHBT technology also needs to achieve low turn-on voltage V/sub ce,sat/, low knee voltage V/sub k/, high breakdown voltages BVCEO, BVCBO, and on-state breakdown voltage. Furthermore, excellent device yield, high circuit-performance and uniformity are required. Optimization of all these parameters is critical for any given technology to be practically useful. In this paper, we report on a high-yield, high performance InP/InGaAs DHBT process with excellent uniformity and reproducibility.","PeriodicalId":142875,"journal":{"name":"24th Annual Technical Digest Gallium Arsenide Integrated Circuit (GaAs IC) Symposiu","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125851261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
87 GHz static frequency divider in an InP-based mesa DHBT technology 基于inp的台式DHBT技术中的87 GHz静态分频器
S. Krishnan, Z. Griffith, M. Urteaga, Y. Wei, D. Scott
{"title":"87 GHz static frequency divider in an InP-based mesa DHBT technology","authors":"S. Krishnan, Z. Griffith, M. Urteaga, Y. Wei, D. Scott","doi":"10.1109/GAAS.2002.1049081","DOIUrl":"https://doi.org/10.1109/GAAS.2002.1049081","url":null,"abstract":"Reports on a static frequency divider with a maximum clock frequency of 87 GHz in a mesa InP/InGaAs/InP DHBT technology. The divider is operational at all tested frequencies between 4 and 87 GHz and dissipated 700 mW of power from a -4.5V supply.","PeriodicalId":142875,"journal":{"name":"24th Annual Technical Digest Gallium Arsenide Integrated Circuit (GaAs IC) Symposiu","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129105584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Monolithic integration of In/sub 0.53/Ga/sub 0.47/As photodiodes and In/sub 0.53/Ga/sub 0.47/As/In/sub 0.52/Al/sub 0.48/As HEMTs on GaAs substrates for long wavelength OEIC applications In/sub 0.53/Ga/sub 0.47/As光电二极管和In/sub 0.53/Ga/sub 0.47/As/In/sub 0.52/Al/sub 0.48/As hemt在GaAs衬底上的单片集成,用于长波OEIC应用
J. Jang, G. Cueva, R. Sankaralingam, P. Fay, W. Hoke, I. Adesida
{"title":"Monolithic integration of In/sub 0.53/Ga/sub 0.47/As photodiodes and In/sub 0.53/Ga/sub 0.47/As/In/sub 0.52/Al/sub 0.48/As HEMTs on GaAs substrates for long wavelength OEIC applications","authors":"J. Jang, G. Cueva, R. Sankaralingam, P. Fay, W. Hoke, I. Adesida","doi":"10.1109/GAAS.2002.1049028","DOIUrl":"https://doi.org/10.1109/GAAS.2002.1049028","url":null,"abstract":"Metamorphic long wavelength double heterojunction photodiodes with In/sub 0.53/Ga/sub 0.47/As photo-absorption layer and In/sub 0.53/Ga/sub 0.47/As/In/sub 0.52/Al/sub 0.48/As metamorphic HEMTs were realized on the same GaAs substrate. The photodiodes exhibited high speed and low leakage characteristics and the performance of HEMTs beneath the photodiode layers were also comparable to those fabricated on HEMT-only heterostructures.","PeriodicalId":142875,"journal":{"name":"24th Annual Technical Digest Gallium Arsenide Integrated Circuit (GaAs IC) Symposiu","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129847801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 23/3-dB dual-gain low-noise amplifier for 5-GHz-band wireless applications 一款23/ 3db双增益低噪声放大器,适用于5ghz波段无线应用
Y. Aoki, N. Hayama, M. Fujii, H. Hida
{"title":"A 23/3-dB dual-gain low-noise amplifier for 5-GHz-band wireless applications","authors":"Y. Aoki, N. Hayama, M. Fujii, H. Hida","doi":"10.1109/GAAS.2002.1049059","DOIUrl":"https://doi.org/10.1109/GAAS.2002.1049059","url":null,"abstract":"We have developed a wide-dynamic-range low-noise amplifier (LNA) based on InGaP/GaAs hetero bipolar transistors (HBTs) for 5-GHz-band wireless applications. With no external matching components, this dual-gain LNA (with a 20-dB gain attenuation function) has a very high performance; namely, a noise figure (NF) of 2.3 dB, a gain of 23 dB, an output 1-dB compression point(P/sub 1dB/) of 9.8 dBm, and a DC power consumption (P/sub dc/) of 28 mW at 3.0 V. Its figure of merit, defined as (gain/NF)/spl middot/(P/sub 1dB//Pd/sub dc/), is 3.3, which is the highest value in the C-band to date.","PeriodicalId":142875,"journal":{"name":"24th Annual Technical Digest Gallium Arsenide Integrated Circuit (GaAs IC) Symposiu","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133726041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
InP DHBT technology and design for 40 Gbit/s full-rate-clock communication circuits 采用DHBT技术设计40gbit /s全速率时钟通信电路
J. Godin, M. Riet, S. Blayac, P. Berdaguer, V. Dhalluin, F. Alexandre, M. Kahn, A. Pinquier, A. Kasbari, J. Moulu, A. Konczykowska
{"title":"InP DHBT technology and design for 40 Gbit/s full-rate-clock communication circuits","authors":"J. Godin, M. Riet, S. Blayac, P. Berdaguer, V. Dhalluin, F. Alexandre, M. Kahn, A. Pinquier, A. Kasbari, J. Moulu, A. Konczykowska","doi":"10.1109/GAAS.2002.1049063","DOIUrl":"https://doi.org/10.1109/GAAS.2002.1049063","url":null,"abstract":"In this paper, we present our InP DHBT technology with improved performances, yield and uniformity; and some new design tools, both of which have allowed us to achieve 40+ Gbit/s full-rate-clock circuits, such as the D-flip-flop. These circuits have been characterized and packaged.","PeriodicalId":142875,"journal":{"name":"24th Annual Technical Digest Gallium Arsenide Integrated Circuit (GaAs IC) Symposiu","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133847467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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