40gb /s集成差分PIN+TIA，采用InP SHBT技术进行直流偏置控制

24th Annual Technical Digest Gallium Arsenide Integrated Circuit (GaAs IC) Symposiu Pub Date : 2002-12-10 DOI:10.1109/GAAS.2002.1049029

D. Caruth, S. Shen, D. Chan, M. Feng, J. Schutt-Ainé

{"title":"40gb /s集成差分PIN+TIA，采用InP SHBT技术进行直流偏置控制","authors":"D. Caruth, S. Shen, D. Chan, M. Feng, J. Schutt-Ainé","doi":"10.1109/GAAS.2002.1049029","DOIUrl":null,"url":null,"abstract":"Describes the design and measured performance of a 40 Gb/s integrated differential PIN+TIA with offset control using InP SHBT technology. The circuit was designed to handle large average optical input power levels (>5 dBm) encountered in short-haul networks where optical gain control may not be available or economical.","PeriodicalId":142875,"journal":{"name":"24th Annual Technical Digest Gallium Arsenide Integrated Circuit (GaAs IC) Symposiu","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":"{\"title\":\"A 40 Gb/s integrated differential PIN+TIA with DC offset control using InP SHBT technology\",\"authors\":\"D. Caruth, S. Shen, D. Chan, M. Feng, J. Schutt-Ainé\",\"doi\":\"10.1109/GAAS.2002.1049029\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Describes the design and measured performance of a 40 Gb/s integrated differential PIN+TIA with offset control using InP SHBT technology. The circuit was designed to handle large average optical input power levels (>5 dBm) encountered in short-haul networks where optical gain control may not be available or economical.\",\"PeriodicalId\":142875,\"journal\":{\"name\":\"24th Annual Technical Digest Gallium Arsenide Integrated Circuit (GaAs IC) Symposiu\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-12-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"19\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"24th Annual Technical Digest Gallium Arsenide Integrated Circuit (GaAs IC) Symposiu\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/GAAS.2002.1049029\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"24th Annual Technical Digest Gallium Arsenide Integrated Circuit (GaAs IC) Symposiu","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GAAS.2002.1049029","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 19

摘要

介绍了采用InP SHBT技术的40gb /s集成差分PIN+TIA的设计和测量性能。该电路被设计用于处理在短距离网络中遇到的大平均光输入功率电平(> - 5dbm)，在这种情况下光增益控制可能不可用或不经济。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A 40 Gb/s integrated differential PIN+TIA with DC offset control using InP SHBT technology

Describes the design and measured performance of a 40 Gb/s integrated differential PIN+TIA with offset control using InP SHBT technology. The circuit was designed to handle large average optical input power levels (>5 dBm) encountered in short-haul networks where optical gain control may not be available or economical.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

24th Annual Technical Digest Gallium Arsenide Integrated Circuit (GaAs IC) Symposiu

自引率

0.00%

发文量