采用DHBT技术设计40gbit /s全速率时钟通信电路

24th Annual Technical Digest Gallium Arsenide Integrated Circuit (GaAs IC) Symposiu Pub Date : 2002-12-10 DOI:10.1109/GAAS.2002.1049063

J. Godin, M. Riet, S. Blayac, P. Berdaguer, V. Dhalluin, F. Alexandre, M. Kahn, A. Pinquier, A. Kasbari, J. Moulu, A. Konczykowska

{"title":"采用DHBT技术设计40gbit /s全速率时钟通信电路","authors":"J. Godin, M. Riet, S. Blayac, P. Berdaguer, V. Dhalluin, F. Alexandre, M. Kahn, A. Pinquier, A. Kasbari, J. Moulu, A. Konczykowska","doi":"10.1109/GAAS.2002.1049063","DOIUrl":null,"url":null,"abstract":"In this paper, we present our InP DHBT technology with improved performances, yield and uniformity; and some new design tools, both of which have allowed us to achieve 40+ Gbit/s full-rate-clock circuits, such as the D-flip-flop. These circuits have been characterized and packaged.","PeriodicalId":142875,"journal":{"name":"24th Annual Technical Digest Gallium Arsenide Integrated Circuit (GaAs IC) Symposiu","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"InP DHBT technology and design for 40 Gbit/s full-rate-clock communication circuits\",\"authors\":\"J. Godin, M. Riet, S. Blayac, P. Berdaguer, V. Dhalluin, F. Alexandre, M. Kahn, A. Pinquier, A. Kasbari, J. Moulu, A. Konczykowska\",\"doi\":\"10.1109/GAAS.2002.1049063\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we present our InP DHBT technology with improved performances, yield and uniformity; and some new design tools, both of which have allowed us to achieve 40+ Gbit/s full-rate-clock circuits, such as the D-flip-flop. These circuits have been characterized and packaged.\",\"PeriodicalId\":142875,\"journal\":{\"name\":\"24th Annual Technical Digest Gallium Arsenide Integrated Circuit (GaAs IC) Symposiu\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-12-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"24th Annual Technical Digest Gallium Arsenide Integrated Circuit (GaAs IC) Symposiu\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/GAAS.2002.1049063\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"24th Annual Technical Digest Gallium Arsenide Integrated Circuit (GaAs IC) Symposiu","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GAAS.2002.1049063","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 8

摘要

在本文中，我们提出了我们的InP DHBT技术，提高了性能，收率和均匀性;以及一些新的设计工具，这两者都使我们能够实现40+ Gbit/s的全速率时钟电路，例如d触发器。对这些电路进行了表征和封装。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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InP DHBT technology and design for 40 Gbit/s full-rate-clock communication circuits

In this paper, we present our InP DHBT technology with improved performances, yield and uniformity; and some new design tools, both of which have allowed us to achieve 40+ Gbit/s full-rate-clock circuits, such as the D-flip-flop. These circuits have been characterized and packaged.

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来源期刊

24th Annual Technical Digest Gallium Arsenide Integrated Circuit (GaAs IC) Symposiu

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