A 40 Gb/s integrated differential PIN+TIA with DC offset control using InP SHBT technology

Abstract

Describes the design and measured performance of a 40 Gb/s integrated differential PIN+TIA with offset control using InP SHBT technology. The circuit was designed to handle large average optical input power levels (>5 dBm) encountered in short-haul networks where optical gain control may not be available or economical.