InP DHBT technology and design for 40 Gbit/s full-rate-clock communication circuits

24th Annual Technical Digest Gallium Arsenide Integrated Circuit (GaAs IC) Symposiu Pub Date : 2002-12-10 DOI:10.1109/GAAS.2002.1049063

J. Godin, M. Riet, S. Blayac, P. Berdaguer, V. Dhalluin, F. Alexandre, M. Kahn, A. Pinquier, A. Kasbari, J. Moulu, A. Konczykowska

引用次数: 8

Abstract

In this paper, we present our InP DHBT technology with improved performances, yield and uniformity; and some new design tools, both of which have allowed us to achieve 40+ Gbit/s full-rate-clock circuits, such as the D-flip-flop. These circuits have been characterized and packaged.

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采用DHBT技术设计40gbit /s全速率时钟通信电路

在本文中，我们提出了我们的InP DHBT技术，提高了性能，收率和均匀性;以及一些新的设计工具，这两者都使我们能够实现40+ Gbit/s的全速率时钟电路，例如d触发器。对这些电路进行了表征和封装。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

24th Annual Technical Digest Gallium Arsenide Integrated Circuit (GaAs IC) Symposiu

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