2020 21st International Conference on Electronic Packaging Technology (ICEPT)最新文献

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Facile Fabrication of Silicon Carbide Spheres and Its Application in Polymer Composites with Enhanced Thermal Conductivity 碳化硅球的简易制备及其在增强导热聚合物复合材料中的应用
2020 21st International Conference on Electronic Packaging Technology (ICEPT) Pub Date : 2020-08-01 DOI: 10.1109/ICEPT50128.2020.9202640
Yimin Yao, Feiyang Huang, Xuebing Bai, Xiaoliang Zeng, Jianbin Xu, R. Sun, Fei Deng, Peipei Xin
{"title":"Facile Fabrication of Silicon Carbide Spheres and Its Application in Polymer Composites with Enhanced Thermal Conductivity","authors":"Yimin Yao, Feiyang Huang, Xuebing Bai, Xiaoliang Zeng, Jianbin Xu, R. Sun, Fei Deng, Peipei Xin","doi":"10.1109/ICEPT50128.2020.9202640","DOIUrl":"https://doi.org/10.1109/ICEPT50128.2020.9202640","url":null,"abstract":"There is an urgent requirement of satisfied thermal management materials to help efficiently diffuse the accumulated heat in modern electronics. The high-loading addition of ceramic filler into polymer is able to significantly enhance the thermal conductivity but inevitably causes serious degradation of mechanical properties. Thus, how to achieve desired thermal conductivity at relatively low filler content still maintains challenging. In this study, we report on a facile strategy to fabricate silicon carbide spheres (SiCSs), which can be applied as efficient fillers to construct three-dimensional (3D) filler skeleton in the polymer matrix. The obtained silicon carbide spheres exhibit fancy sea urchin-like microstructure with obvious radiating pattern. The polymer composites were finally prepared by adding the SiCSs into epoxy resin matrix. A satisfactory thermal conductivity of 0.91 Wm-1K-1 with the addition of 4.6 vol% SiCSs was achieved in the obtained composites. Moreover, the final thermal conductivity can be easily regulated by varying the added number of SiCSs. The above results illustrate that the SiCSs/epoxy composites exhibit high potential for application in thermal management field.","PeriodicalId":136777,"journal":{"name":"2020 21st International Conference on Electronic Packaging Technology (ICEPT)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116581290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Research on ultra-low noise LDO measurement technology 超低噪声LDO测量技术研究
2020 21st International Conference on Electronic Packaging Technology (ICEPT) Pub Date : 2020-08-01 DOI: 10.1109/ICEPT50128.2020.9202581
Bao Xingrun, Xiang Fei
{"title":"Research on ultra-low noise LDO measurement technology","authors":"Bao Xingrun, Xiang Fei","doi":"10.1109/ICEPT50128.2020.9202581","DOIUrl":"https://doi.org/10.1109/ICEPT50128.2020.9202581","url":null,"abstract":"In recent years, with the increasing requirements of high-tech industry for the performance of power supply, especially for the improvement of power noise, the traditional LDO has been unable to meet the system requirements, and it is urgent to improve the system performance with ultra-low noise LDO. Ultra low noise LDO mainly supplies power for noise sensitive signal processing system, including RF, PLL / VCO, RF mixer and modulator, ADC / DAC and high-precision sensor. The power integration noise index of some systems has reached below 5µVRMS. How to evaluate the low noise level of the device is a difficult problem. The domestic LDO noise measurement mainly relies on the traditional measurement methods, which can barely measure and evaluate the conventional LDO noise in theory, but it is difficult to accurately evaluate the ultra-low noise LDO due to the limitations of measurement methods, external environment and other factors, which brings great trouble to the research, development and application of ultra-low noise LDO. How to accurately evaluate the noise index is very important for the research, development and application Yes. In view of the fact that there is no special LDO noise measuring instrument and equipment in the industry, especially the difficulty of ultra-low noise evaluation and measurement, this paper puts forward the system framework, noise measuring circuit, system design requirements and environmental requirements of ultra-low noise measurement through research. The measurement method and system framework have been successfully applied to a number of ultra-low noise LDO chips with high reference value It has certain practical significance.","PeriodicalId":136777,"journal":{"name":"2020 21st International Conference on Electronic Packaging Technology (ICEPT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130993065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
In-situ study the morphology, growth kinetics and mechanism of Cu6Sn5 at the SnAgCu/Cu soldering interfaces during the cooling stage 现场研究了冷却阶段SnAgCu/Cu焊接界面处Cu6Sn5的形貌、生长动力学和机理
2020 21st International Conference on Electronic Packaging Technology (ICEPT) Pub Date : 2020-08-01 DOI: 10.1109/ICEPT50128.2020.9202589
Bingfeng Guo
{"title":"In-situ study the morphology, growth kinetics and mechanism of Cu6Sn5 at the SnAgCu/Cu soldering interfaces during the cooling stage","authors":"Bingfeng Guo","doi":"10.1109/ICEPT50128.2020.9202589","DOIUrl":"https://doi.org/10.1109/ICEPT50128.2020.9202589","url":null,"abstract":"In this paper, the IMC (Cu6Sn5) morphology evolution was observed by using Shanghai Light Source Synchrotron Radiation (SSRF) and high-pressure air technology. Comparing with complete reflow experiments, IMC growth data during the cooling stage was obtained to study the growth process of typical Cu6Sn5 grain morphology evolution. The results are as follows: (1) The morphology of interfacial Cu6Sn5 during the cooling stage is changed from scallop to facet or prism. Liquid channels between Cu6Sn5 grains were also in-situ observed. The presence of liquid channels increases the diffusion flux of Cu grain boundaries and reduces the IMC growth activation energy, indicating that the addition of Ag can hinder the lateral merging of Cu6Sn5 grain boundary during the heat preservation. Simultaneously, the channels also promote the vertical growth of Cu6Sn5 grains to get a smaller aspect ratio at Sn-3.5Ag-0.7Cu(SAC3507)/Cu interface than Sn/Cu. (2) The growth thickness of IMC during the cooling stage follows the rule of h=kt, which is the reaction control mechanism of the Cu precipitation interface. (3) The interfacial Cu6Sn5 growth during the cooling stage is affected by the pinning effect of Ag3Sn nanoparticles and the Cu precipitation flux. Finally, under the same soldering conditions, the Cu6Sn5 thickness at SAC3507/Cu soldering interface during the cooling stage is thicker than Sn/Cu.","PeriodicalId":136777,"journal":{"name":"2020 21st International Conference on Electronic Packaging Technology (ICEPT)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131278010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The Analysis of Vertical Cross Talk on Top Emission AMOLED 顶发射AMOLED的垂直串扰分析
2020 21st International Conference on Electronic Packaging Technology (ICEPT) Pub Date : 2020-08-01 DOI: 10.1109/ICEPT50128.2020.9201921
Zhibin Han, Jianxin Liu, Gary Chaw, Shengdong Zhang
{"title":"The Analysis of Vertical Cross Talk on Top Emission AMOLED","authors":"Zhibin Han, Jianxin Liu, Gary Chaw, Shengdong Zhang","doi":"10.1109/ICEPT50128.2020.9201921","DOIUrl":"https://doi.org/10.1109/ICEPT50128.2020.9201921","url":null,"abstract":"In Top Emission AMOLED pixel, data line will overlap with anode layer, resulting in large parasitic capacitance Cpd (Capacitance between dateline and pixel anode). Therefore, we conduct electrical simulation analysis on cross-talk caused by dataline. Unlike LCD, The parasitic capacitance did not cause obvious cross-talk, while vertical cross-talk was mainly caused by the leakage of TFT, and the effect of TFT leakage could be improved by adjusting pixel storage capacitance.","PeriodicalId":136777,"journal":{"name":"2020 21st International Conference on Electronic Packaging Technology (ICEPT)","volume":"606 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132151563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Interfacial microstructure of NiPt/SnIn/Cu sputtering target assembly after soldering NiPt/SnIn/Cu溅射靶组件焊接后的界面微观结构
2020 21st International Conference on Electronic Packaging Technology (ICEPT) Pub Date : 2020-08-01 DOI: 10.1109/ICEPT50128.2020.9201936
Zhichao Meng, M. Wen, Zhi-Quan Liu
{"title":"Interfacial microstructure of NiPt/SnIn/Cu sputtering target assembly after soldering","authors":"Zhichao Meng, M. Wen, Zhi-Quan Liu","doi":"10.1109/ICEPT50128.2020.9201936","DOIUrl":"https://doi.org/10.1109/ICEPT50128.2020.9201936","url":null,"abstract":"With the miniaturization of electronic devices, the application of thin film materials in electronic devices is becoming more and more widespread. Sputter coating to prepare film material has attracted attention because of its good film formation quality, high deposition efficiency and controllable thickness. The quality of film material is mostly determined by target material. Generally, the target material is fixed to the back plate by welding or mechanical connection method, to form a target back plate assembly. The target back plate should not only have a reliable mechanical connection, but also have good thermal conductivity to ensure heating dissipation during the sputtering process. In this paper, the NiPt alloy target and Cu backplate is soldered together by Sn/In solder to form the target backplate assembly. The microstructure and morphology of the soldering interface between NiPt target and Cu backplate is investigated. The composition of the formed intermetallic compound (IMC) is analyzed, which is significant for improving the reliability of large-size metal targets backplate and ensuring the quality of the soldering interface.","PeriodicalId":136777,"journal":{"name":"2020 21st International Conference on Electronic Packaging Technology (ICEPT)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134502162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multi-chip Stacking with Fine Pitch μbumps and TSVs for Heterogeneous Integration 基于小间距μ凸点的多芯片堆叠与tsv异质集成
2020 21st International Conference on Electronic Packaging Technology (ICEPT) Pub Date : 2020-08-01 DOI: 10.1109/ICEPT50128.2020.9202456
Yangyang Yan, Guojun Wang, Hanqiang Su, Fengwei Dai, P. Sun, Liqiang Cao
{"title":"Multi-chip Stacking with Fine Pitch μbumps and TSVs for Heterogeneous Integration","authors":"Yangyang Yan, Guojun Wang, Hanqiang Su, Fengwei Dai, P. Sun, Liqiang Cao","doi":"10.1109/ICEPT50128.2020.9202456","DOIUrl":"https://doi.org/10.1109/ICEPT50128.2020.9202456","url":null,"abstract":"Multichip stacking technique is becoming more and more essential for the development of advanced 3D heterogeneous systems with TSVs in the era of AI and 5G. Motivated by the desire to realize such future system integrations, we have developed an advanced multichip stacking prototype module which contains four dies stacking on an interposer with fine pitch copper pillar micro-bumps and TSVs. The minimum diameter and pitch of the micro-bumps employed was with 18μm and 30μm, respectively. While, the diameter and pitch of the TSVs employed was with 10μm and 100μm, respectively. The DC resistance of a long serial signal chain which transfers from the organic substrate to Die_3, then to Die_2, then to silicon interposer, then to Die1_1, then to Die1_2, and finally back to the organic substrate, was measured in the rage of 6~9Ω, indicating a good stacking uniformity. The proposed multichip stacking technique is expected to be applied to the development of future 3D heterogeneous integration applications.","PeriodicalId":136777,"journal":{"name":"2020 21st International Conference on Electronic Packaging Technology (ICEPT)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133008076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Research on the Board-level Reliability of Ceramic Column Grid Array Packaging Component 陶瓷柱栅阵列封装元件板级可靠性研究
2020 21st International Conference on Electronic Packaging Technology (ICEPT) Pub Date : 2020-08-01 DOI: 10.1109/ICEPT50128.2020.9202947
Yongxin Zhu, Hongmin Liu, Shuo Chang
{"title":"Research on the Board-level Reliability of Ceramic Column Grid Array Packaging Component","authors":"Yongxin Zhu, Hongmin Liu, Shuo Chang","doi":"10.1109/ICEPT50128.2020.9202947","DOIUrl":"https://doi.org/10.1109/ICEPT50128.2020.9202947","url":null,"abstract":"With the development of universe space exploration, the Ceramic column grid array (CCGA) package is widely used for its excellent performance for the field programmable gate array (FPGA) logic device. Generally, the board level reliability of this device is evaluated by ways of vibration following thermal cycling test in order to simulate the condition experienced by the spacecraft during launching and on-orbit operation stage. In this paper, a print circuit board (pcb) soldering a CCGA component with 1140 I/Os was designed and the thermal shock and vibration test were conducted. The test board comprises series of light emitting diodes (LEDs) which can be lighted up when downloading program into the CCGA component and that can reflect the reliability of solder joint or column. The results show that some LEDs were went out after thermal shock following vibration test and the failure was induced by the vibration rather than the thermal shock based on the other two boards test result. In addition, the Z direction vibration that parallel to the column was responsible for failure rather than the X and Y direction. On the other hand, the crack was found on columns near the rib stiffener and its distribution is disordered, some near the pcb side and other near the component side. At last, a board with new structure was designed and the same test was conducted. The electric property had no change before and after the thermal shock following vibration test and no crack was found from the cross section analysis which means the structure design has an important effect on the CCGA component vibration reliability.","PeriodicalId":136777,"journal":{"name":"2020 21st International Conference on Electronic Packaging Technology (ICEPT)","volume":"222 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133489074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Thermal stress failure analysis of power diode SMBF package 功率二极管SMBF封装热应力失效分析
2020 21st International Conference on Electronic Packaging Technology (ICEPT) Pub Date : 2020-08-01 DOI: 10.1109/ICEPT50128.2020.9202545
Yuyu Peng, Wei Gao, Qiao Guo, Bo Zhang
{"title":"Thermal stress failure analysis of power diode SMBF package","authors":"Yuyu Peng, Wei Gao, Qiao Guo, Bo Zhang","doi":"10.1109/ICEPT50128.2020.9202545","DOIUrl":"https://doi.org/10.1109/ICEPT50128.2020.9202545","url":null,"abstract":"With the development of power devices, the thermal reliability of power devices has become a research hot spot. The research object of this paper is the power diode of SMBF package. Through X-ray scanning and resin removal observation, it can be concluded that the excessive thermal stress of SMBF package may be the cause of its failure. Using ANSYS Workbench software simulation, the results show that the reduction of thermal expansion coefficient of resin can reduce the thermal stress. When the coefficient of thermal expansion is reduced from 11*10-6C-1 to 9*10-6C-1, the maximum shape variable of the device is reduced by 80.72%. When the thermal conductivity of the resin is reduced from 4.75W/(m*C) to 5.58W/(m*C), the junction temperature is reduced by 7.76%.","PeriodicalId":136777,"journal":{"name":"2020 21st International Conference on Electronic Packaging Technology (ICEPT)","volume":"239 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131691089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Backside ultraviolet illumination enhanced metal-assisted chemical etching for high-aspect-ratio silicon microstructures 背面紫外光照射增强金属辅助化学蚀刻高纵横比硅微结构
2020 21st International Conference on Electronic Packaging Technology (ICEPT) Pub Date : 2020-08-01 DOI: 10.1109/ICEPT50128.2020.9202685
D. Shi, Yun Chen, Yanhui Chen, Maoxiang Hou, Xun Chen, Xin Chen, Jian Gao, Yunbo He
{"title":"Backside ultraviolet illumination enhanced metal-assisted chemical etching for high-aspect-ratio silicon microstructures","authors":"D. Shi, Yun Chen, Yanhui Chen, Maoxiang Hou, Xun Chen, Xin Chen, Jian Gao, Yunbo He","doi":"10.1109/ICEPT50128.2020.9202685","DOIUrl":"https://doi.org/10.1109/ICEPT50128.2020.9202685","url":null,"abstract":"High-aspect-ratio silicon microstructures have been widely used in micro-electro-mechanical systems, microelectronics cooling and electronic packaging. Recently, metal-assisted chemical etching (MACE) was proved to be an effective alternative to achieve various microstructures. In traditional MACE, holes are generated by the metal catalyst induced reduction of the etchant. However, when the aspect ratio of the fabricated microstructure increases, the mobility of the reactants and the resultant are correspondingly impeded, resulting in insufficient holes, thus, the etching rate decreases significantly. In this study, back-side ultraviolet (UV) illumination in MACE was proposed to provide additional holes. A novel experimental setup was designed and developed. Compared with the traditional MACE, the back-side UV illumination enhanced MACE can significantly enhance the etching rate and fabricate root-like Si microstructures. It is revealed that the holes which are generated by the back-side UV illuminating area can diffuse through bulk Si, accumulate in the etchant side because of the trapping of the pore tip, and participate in the etching reaction. By tuning the applied UV power, root-like microstructures with its width varying from 4.9 to 63.8 μm and depth varying from 13.7 to 47.4 μm were achieved. This study can provide useful insights for developing novel Si processing techniques and fabricating various microstructures.","PeriodicalId":136777,"journal":{"name":"2020 21st International Conference on Electronic Packaging Technology (ICEPT)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132169800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Influence of Titanium on Low Temperature Active Bonding of Quartz Glass with Bi42Sn2Ag2Ti(Ce,Ga) Alloy Filler 钛对Bi42Sn2Ag2Ti(Ce,Ga)合金填充石英玻璃低温活性键合的影响
2020 21st International Conference on Electronic Packaging Technology (ICEPT) Pub Date : 2020-08-01 DOI: 10.1109/ICEPT50128.2020.9202599
Dong Chen, LanXian Cheng, X. Yue, Guoyuan Li
{"title":"Influence of Titanium on Low Temperature Active Bonding of Quartz Glass with Bi42Sn2Ag2Ti(Ce,Ga) Alloy Filler","authors":"Dong Chen, LanXian Cheng, X. Yue, Guoyuan Li","doi":"10.1109/ICEPT50128.2020.9202599","DOIUrl":"https://doi.org/10.1109/ICEPT50128.2020.9202599","url":null,"abstract":"Quartz glass is of great technical importance and getting more attractive as a possible candidate for microelectronic packaging substrate or window. In this work, the significant role of active element titanium (Ti) for soldering quartz glass substrates by Bi42Sn2Ag2Ti(Ce,Ga) alloy filler at 170 °C in atmospheric conditions was studied. The time of soldering process was set to be 1, 15, 30, and 60 min, respectively. The microstructures and the dynamic evolution of active element Ti influenced by soldering time were investigated. The glass/solder interface was observed by scanning electron microscopy and the distribution of each element was analyzed by energy dispersive X-ray spectrometry. Results show that the bonding could be achieved by adsorption and segregation of Ti at the interface between quartz glass and active solder. The adsorption and segregation of the Ti element at the quartz glass/solder interface was analyzed theoretically, and the interfacial reaction has been investigated. The understanding of diffusion kinetics of Ti element can further explain the mechanism of active soldering.","PeriodicalId":136777,"journal":{"name":"2020 21st International Conference on Electronic Packaging Technology (ICEPT)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122347678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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