Multi-chip Stacking with Fine Pitch μbumps and TSVs for Heterogeneous Integration

Abstract

Multichip stacking technique is becoming more and more essential for the development of advanced 3D heterogeneous systems with TSVs in the era of AI and 5G. Motivated by the desire to realize such future system integrations, we have developed an advanced multichip stacking prototype module which contains four dies stacking on an interposer with fine pitch copper pillar micro-bumps and TSVs. The minimum diameter and pitch of the micro-bumps employed was with 18μm and 30μm, respectively. While, the diameter and pitch of the TSVs employed was with 10μm and 100μm, respectively. The DC resistance of a long serial signal chain which transfers from the organic substrate to Die_3, then to Die_2, then to silicon interposer, then to Die1_1, then to Die1_2, and finally back to the organic substrate, was measured in the rage of 6~9Ω, indicating a good stacking uniformity. The proposed multichip stacking technique is expected to be applied to the development of future 3D heterogeneous integration applications.