IEEE Transactions on Very Large Scale Integration (VLSI) Systems最新文献_第5页

Metastable-Dither-Based Digital Background Calibration of Interstage Gain Nonlinearity in Pipelined SAR ADC 基于亚稳抖动的流水式SAR ADC级间增益非线性数字背景校正

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-03-17 DOI: 10.1109/TVLSI.2025.3544825

Le Chen;Yue Cao;Lin Ling;Shubin Liu;Haolin Han

引用次数: 0

An RRAM-Based Computing-in-Memory Macro With Low-Power Readout/Hold Circuits and Activation Differential Strategy for AdderNet AdderNet中基于rram的低功耗读出/保持电路和激活差分策略的内存宏

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-03-17 DOI: 10.1109/TVLSI.2025.3546684

Zhihang Qian;Shengzhe Yan;Zhuoyu Dai;Zeyu Guo;Zhaori Cong;Yifan He;Chunmeng Dou;Feng Zhang;Jinshan Yue;Yongpan Liu

{"title":"An RRAM-Based Computing-in-Memory Macro With Low-Power Readout/Hold Circuits and Activation Differential Strategy for AdderNet","authors":"Zhihang Qian;Shengzhe Yan;Zhuoyu Dai;Zeyu Guo;Zhaori Cong;Yifan He;Chunmeng Dou;Feng Zhang;Jinshan Yue;Yongpan Liu","doi":"10.1109/TVLSI.2025.3546684","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3546684","url":null,"abstract":"AdderNet is an innovative neural network (NN) structure that substitutes multiplications with additions in convolutional operations, while computing-in-memory (CIM) is an efficient architecture that tackles the memory bottleneck for von Neumann architectures. Previous work has explored the SRAM-based CIM AdderNet circuits and demonstrates high energy efficiency. However, it still suffers low storage density, repetitive readout, and redundant comparisons. In this brief, an RRAM-based CIM macro is proposed for efficient AdderNet with the following innovations. First, RRAM cells are adopted to replace SRAM for high-density weight storage. A low-power readout and hold circuit is proposed to save redundant read power of weight data held for multiple cycles. Second, an 8-bit comparator with an early-stop strategy is proposed to compare 8-bit activations and weights in one cycle. Third, an activation (ACT) differential strategy is proposed to reduce redundant comparisons. The proposed 28-nm RRAM CIM macro achieves 12.8-TOPS/mm2 peak area efficiency and 126-TOPS/W peak energy efficiency, which is <inline-formula> <tex-math>$3.0times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$1.2times $ </tex-math></inline-formula> compared with the state-of-the-art AdderNet CIM macro.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 7","pages":"2029-2033"},"PeriodicalIF":2.8,"publicationDate":"2025-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144519288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Information Leakage Through Physical Layer Supply Voltage Coupling Vulnerability 通过物理层电源电压耦合漏洞泄露信息

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-03-17 DOI: 10.1109/TVLSI.2025.3545804

Sahan Sanjaya;Aruna Jayasena;Prabhat Mishra

{"title":"Information Leakage Through Physical Layer Supply Voltage Coupling Vulnerability","authors":"Sahan Sanjaya;Aruna Jayasena;Prabhat Mishra","doi":"10.1109/TVLSI.2025.3545804","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3545804","url":null,"abstract":"Power side-channel attacks are widely known for extracting information from data processed within a device while assuming that an attacker has physical access or the ability to modify the device. In this article, we introduce a novel side-channel vulnerability that leaks data-dependent power variations through physical layer supply voltage coupling (PSVC). Unlike traditional power side-channel attacks, the proposed vulnerability allows an adversary to mount an attack and extract information without modifying the device. In addition, unlike existing power-based remote attacks on field-programmable gate arrays (FPGAs), the PSVC vulnerability applies to both on-chip and on-board attacks. We assess the effectiveness of the PSVC vulnerability through three case studies, demonstrating several end-to-end attacks on general-purpose microcontrollers with varying adversary capabilities. These case studies provide evidence for the existence of the PSVC vulnerability, its applicability to on-chip as well as on-board side-channel attacks, and how it can eliminate the need for physical access to the target device, making it applicable to any off-the-shelf hardware. Our experiments also reveal that designing devices to operate at the lowest operational voltage significantly reduces the risk of PSVC side-channel vulnerability.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 6","pages":"1715-1728"},"PeriodicalIF":2.8,"publicationDate":"2025-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144117270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 12-bit 2-GS/s Pipeline ADC in 28-nm CMOS With Linear-Error Self-Calibration 具有线性误差自校准的28纳米CMOS 12位2-GS/s流水线ADC

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-03-17 DOI: 10.1109/TVLSI.2025.3545364

Yabo Ni;Lu Liu;Yong Zhang;Tao Zhu

{"title":"A 12-bit 2-GS/s Pipeline ADC in 28-nm CMOS With Linear-Error Self-Calibration","authors":"Yabo Ni;Lu Liu;Yong Zhang;Tao Zhu","doi":"10.1109/TVLSI.2025.3545364","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3545364","url":null,"abstract":"This article discusses a 12-bit 2-GS/s pipeline analog-to-digital converter (ADC). A self-calibration technique is employed to correct linear errors due to capacitor mismatches and interstage gain errors (IGEs). To counteract the effects of power supply and temperature variations, the first three stages of the ADC are equipped with least-mean-squares (LMS) IGE background calibrations, enhanced by the injection of a 1-bit dither into these stages. The computational engines designed for background calibration were reused for self-calibration, simplifying the overall design. An improved integrated input buffer drives the ADC, achieving a bandwidth of approximately 6.3 GHz, which is essential for high-speed data acquisition and processing. Moreover, a low-power operational transconductance amplifier (OTA) and reference buffer, both operating on a 1.0-V supply, are implemented to minimize the chip’s power consumption. The 12-bit pipeline prototype ADC, fabricated using a 28-nm CMOS process, operates at 2-GS/s with a 1.0-Vpp input signal. It delivers a signal-to-noise-and-distortion ratio (SNDR) of 58.92 dB and a spurious-free dynamic range (SFDR) of 82.23 dB. The ADC core consumes only 180 mW, resulting in a Schreier figure of merits (FoMs) of 156.4 dB.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 6","pages":"1561-1569"},"PeriodicalIF":2.8,"publicationDate":"2025-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144117381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An RRAM Digital Computing-in-Memory Macro With Dual-Mode Multiplication and Maximum Value Rounding Adder Tree 具有双模乘法和最大值舍入加法树的RRAM数字内存计算宏

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-03-17 DOI: 10.1109/TVLSI.2025.3545866

Wang Ye;Hanghang Gao;Zhidao Zhou;Linfang Wang;Weizeng Li;Zhi Li;Jinshan Yue;Xiaoxin Xu;Jianguo Yang;Hongyang Hu;Chunmeng Dou

{"title":"An RRAM Digital Computing-in-Memory Macro With Dual-Mode Multiplication and Maximum Value Rounding Adder Tree","authors":"Wang Ye;Hanghang Gao;Zhidao Zhou;Linfang Wang;Weizeng Li;Zhi Li;Jinshan Yue;Xiaoxin Xu;Jianguo Yang;Hongyang Hu;Chunmeng Dou","doi":"10.1109/TVLSI.2025.3545866","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3545866","url":null,"abstract":"Implementing digital computing-in-memory (DCIM) based on resistive memory (RRAM) faces several critical challenges due to the small signal margin, large device variations, and large energy- and area-overhead induced by the digital adder tree (AT). To address these issues, we propose an RRAM DCIM macro based on the standard foundry one-transistor-one-resistor (1T1R) cell array featuring: 1) dual-mode MAC operation for efficiency- or accuracy-oriented optimization; 2) margin-enhanced digitized unit (MEDU) to amplify the signal ratio; and 3) maximum value rounding AT (MVR-AT) to reduce its power- and area-overhead. A test chip is demonstrated using a 180 nm CMOS process to verify the concept. It achieves a peak energy efficiency (EF) of 63.08 TOPS/W in the efficiency-oriented mode and a minimum error rate of 1.58% in the accuracy-oriented mode. Their combination can meet the requirements of different workloads in AI computing tasks to optimize the overall power consumption with negligible accuracy loss.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 6","pages":"1779-1783"},"PeriodicalIF":2.8,"publicationDate":"2025-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144117388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of Low-Cost and High-Accurate 8-bit Logarithmic Floating-Point Arithmetic Circuits 低成本高精度8位对数浮点运算电路的设计

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-03-15 DOI: 10.1109/TVLSI.2025.3563950

Botao Xiong;Xingyu Shao;Chang Liu;Shize Zhang;Yuchun Chang

{"title":"Design of Low-Cost and High-Accurate 8-bit Logarithmic Floating-Point Arithmetic Circuits","authors":"Botao Xiong;Xingyu Shao;Chang Liu;Shize Zhang;Yuchun Chang","doi":"10.1109/TVLSI.2025.3563950","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3563950","url":null,"abstract":"Recent studies suggest that the 8-bit floating-point (FP) format plays an important role in the deep learning, where the <inline-formula> <tex-math>$E4M3$ </tex-math></inline-formula> (4-bit exponent, 3-bit mantissa) is suited for the natural language processing model and the <inline-formula> <tex-math>$E3M4$ </tex-math></inline-formula> is better on computer vision task. In this brief, the logarithmic number system (LNS) is used to simplify the design of FP8 multipliers and dividers because the multiplication and division can be performed by the addition and subtraction in the logarithmic domain. Furthermore, this brief finds that the 3- and 4-bit logarithmic and anti-logarithmic (Antilog) converters can be effectively realized by {<italic>x, <inline-formula> <tex-math>$x+1$ </tex-math></inline-formula>} and {<italic>x, <inline-formula> <tex-math>$x-1$ </tex-math></inline-formula>}. As a result, compared to the standard <inline-formula> <tex-math>$E4M3$ </tex-math></inline-formula> and <inline-formula> <tex-math>$E3M4$ </tex-math></inline-formula> multipliers, the cell area can be reduced by 32% and 40%. Compared to the standard <inline-formula> <tex-math>$E4M3$ </tex-math></inline-formula> and <inline-formula> <tex-math>$E3M4$ </tex-math></inline-formula> divider, the cell area can be reduced by 61% and 67%. In addition, compared with the INT8-based design, the area of convolution core using proposed multiplier is reduced by 33%. The accuracy loss of the quantized ResNet-50, MobileNet, and ViT-B based on the proposed convolution core are −0.12%, +0.38%, and +0.8%, which are better than the INT8-based design. In the end, the proposed divider can be used in the image change detection. The false rate is slightly reduced from 2.97% to 2.95% compared to the standard <inline-formula> <tex-math>$E3M4$ </tex-math></inline-formula> divider.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 7","pages":"2094-2098"},"PeriodicalIF":2.8,"publicationDate":"2025-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144519396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Flying-Capacitor-Assisted Single-Mode Buck-Boost Converter for Battery-Powered Applications 一种用于电池供电的飞行电容辅助单模降压-升压转换器

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-03-13 DOI: 10.1109/TVLSI.2025.3535698

Sunghae Kim;Taehee Lee;Kunhee Cho;Jaeduk Han

{"title":"A Flying-Capacitor-Assisted Single-Mode Buck-Boost Converter for Battery-Powered Applications","authors":"Sunghae Kim;Taehee Lee;Kunhee Cho;Jaeduk Han","doi":"10.1109/TVLSI.2025.3535698","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3535698","url":null,"abstract":"A single-mode buck-boost converter that generates a 3.3-V power supply from a variable input voltage (<inline-formula> <tex-math>${V} _{mathbf {IN}}$ </tex-math></inline-formula>) range of 2.7–4.2 V for mobile li-ion battery applications is presented. The proposed buck-boost converter employs a switched-capacitor-based buck-converter operation, in which the voltage switching operation is followed by an LC filter. This ensures continuous output current delivery and reduces conduction loss in the inductor. An efficient power-stage structure and its operation are introduced, wherein only one resistive component is connected in series with the inductor during all operation phases. The proposed buck-boost converter has been implemented in a 180-nm BCDMOS process and regulates an output voltage of 3.3 V from a <inline-formula> <tex-math>${V} _{mathbf {IN}}$ </tex-math></inline-formula> range of 2.7–4.2 V by single-mode step-up/down operation. The peak efficiency of 93.4% is achieved at 2.7-V <inline-formula> <tex-math>${V} _{mathbf {IN}}$ </tex-math></inline-formula>, and the peak efficiency above 90% is obtained over the entire <inline-formula> <tex-math>${V} _{mathbf {IN}}$ </tex-math></inline-formula> range.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 5","pages":"1412-1416"},"PeriodicalIF":2.8,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143875231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 14-bit 6.7 MS/s 0.018 mm2 98 μW SAR A/D Converter With On-the-Fly Autocalibration for Array Applications 一种14位6.7 MS/s 0.018 mm2 98 μW SAR A/D转换器，用于阵列应用的动态自动校准

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-03-13 DOI: 10.1109/TVLSI.2025.3557673

Sanjoy Kumar Dey;Arun Kumar Barman;Pawan Sehgal;Mukul Sarkar;Shouribrata Chatterjee

{"title":"A 14-bit 6.7 MS/s 0.018 mm2 98 μW SAR A/D Converter With On-the-Fly Autocalibration for Array Applications","authors":"Sanjoy Kumar Dey;Arun Kumar Barman;Pawan Sehgal;Mukul Sarkar;Shouribrata Chatterjee","doi":"10.1109/TVLSI.2025.3557673","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3557673","url":null,"abstract":"A 14-bit, 6.7 MS/s successive-approximation-register (SAR) A/D converter (ADC) is presented with on-chip autocalibration. An all-digital calibration algorithm with only two extra half-unit capacitors in capacitive DAC (CDAC) enables the ADC to correct itself from mismatch errors. We introduce digital heavy on-the-fly autocalibration, with novel reuse mechanism of existing capacitors, which deliver analog-precision error-correction yielding superior integral-nonlinearity (INL) and spurious free dynamic range (SFDR) at lowest area. The design is limited by thermal noise and not by mismatch error. A self-shut mechanism in dynamic comparator saves power consumption. A 0.018 mm2 test chip in a 65-nm CMOS process consumes <inline-formula> <tex-math>$98~mu $ </tex-math></inline-formula>W power. The calibration improves the INL of the ADC from >20 least significant bit (LSB) to <2.9> <tex-math>${}_{W}$ </tex-math></inline-formula> of 5.8 fJ/conv-step and FoM<inline-formula> <tex-math>${}_{S}$ </tex-math></inline-formula> of 175 dB at an area efficiency (AE) of <inline-formula> <tex-math>$7.2~mu $ </tex-math></inline-formula>m2/code.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 7","pages":"1826-1837"},"PeriodicalIF":2.8,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144519385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hybrid Timestamping Using Crystal and RC Oscillators for Shock-Resistant Precision 使用晶体和RC振荡器的混合时间戳用于抗冲击精度

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-03-11 DOI: 10.1109/TVLSI.2025.3544410

Ehab A. Hamed;Gordy Carichner;Delbert A. Green;Hun-Seok Kim;Inhee Lee

{"title":"Hybrid Timestamping Using Crystal and RC Oscillators for Shock-Resistant Precision","authors":"Ehab A. Hamed;Gordy Carichner;Delbert A. Green;Hun-Seok Kim;Inhee Lee","doi":"10.1109/TVLSI.2025.3544410","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3544410","url":null,"abstract":"Achieving precise timing in miniature systems attached to monarch butterflies is challenging due to the shock sensitivity of crystal oscillators (XOs) and the limited accuracy of <italic>RC oscillators. This brief proposes a hybrid timestamping technique that combines both oscillators as timers to deliver shock-resistant, high-accuracy timing. Three algorithms are evaluated to fine-tune a multiplier (<italic>M), the ratio of the two timers’ speeds, for improved responsiveness and robustness against temperature and voltage variations. The direct ratioing algorithm proves the most effective, determining the correct <italic>M within a single wake-up cycle and reducing time shift error by 145 times in a 12-h test, compared to using an <italic>RC timer alone. This work leverages the existing hardware and introduces new firmware, easily implementable using standard digital circuit design flows, to significantly enhance timing precision and shock resilience in millimeter-scale butterfly tracking systems, making a valuable contribution to the VLSI community.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 7","pages":"2004-2008"},"PeriodicalIF":2.8,"publicationDate":"2025-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144519444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Thermal Simulator for Advanced Packaging and Chiplet-Based Systems 用于先进封装和基于芯片的系统的热模拟器

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-03-11 DOI: 10.1109/TVLSI.2025.3545604

Yousef Safari;Adam Corbier;Dima Al Saleh;Fahad Rahman Amik;Boris Vaisband

{"title":"Thermal Simulator for Advanced Packaging and Chiplet-Based Systems","authors":"Yousef Safari;Adam Corbier;Dima Al Saleh;Fahad Rahman Amik;Boris Vaisband","doi":"10.1109/TVLSI.2025.3545604","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3545604","url":null,"abstract":"Heterogeneous chiplet-based integration is expected to provide performance scalability and cost-effectiveness for the next generation of microelectronic systems. Practical deployment of chiplet-based platforms, however, requires developing novel electronic design automation (EDA) tools that support advanced packaging approaches. Compact thermal simulators are essential EDA tools for the evaluation of design alternatives at the early stages of the design. Developing efficient compact thermal simulators for advanced heterogeneous integration platforms is a key requirement, as the available tools provide limited support for heterogeneity and advanced packaging technologies. ARTSim 2.0, a robust thermal simulator for heterogeneous integration platforms, is presented in this work. ARTSim 2.0 includes three main features, i.e., robust hybrid meshing, modeling of heterogeneous layers, and an efficient solver that utilizes parallel processing. Several case studies on advanced chiplet-based platforms, including TSV-based 3-D integrated circuits (ICs), Intel EMIB, and TSMC InFO_PoP, are conducted to demonstrate the novel capabilities of ARTSim 2.0. The performance of ARTSim 2.0 for both transient and steady-state conditions is compared to results obtained from state-of-the-art finite element method (FEM) tools. Simulation results confirm that the temperature accuracy of the thermal maps that are generated by ARTSim 2.0 is within a maximum error of 1.17% while exhibiting a reduction in runtime of at least two orders of magnitude, as compared to the FEM tools.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 6","pages":"1638-1650"},"PeriodicalIF":2.8,"publicationDate":"2025-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144117239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0