IEEE Transactions on Very Large Scale Integration (VLSI) Systems最新文献_第5页

Stealing AI Model Weights Through Covert Communication Channels 通过隐蔽的通信渠道窃取AI模型权重

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-07-01 Epub Date: 2026-04-27 DOI: 10.1109/TVLSI.2026.3684645

Valentin Barbaza;Alán Rodrigo Díaz-Rizo;Abdelrahman Emad Abdelazim;Emilien Dole;Hassan Aboushady;Spyridon Raptis;Haralampos-G. Stratigopoulos

{"title":"Stealing AI Model Weights Through Covert Communication Channels","authors":"Valentin Barbaza;Alán Rodrigo Díaz-Rizo;Abdelrahman Emad Abdelazim;Emilien Dole;Hassan Aboushady;Spyridon Raptis;Haralampos-G. Stratigopoulos","doi":"10.1109/TVLSI.2026.3684645","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3684645","url":null,"abstract":"Artificial intelligence (AI) models are often regarded as valuable intellectual property due to the high cost of their development, the competitive advantage they provide, and the proprietary techniques involved in their creation. As a result, AI model-stealing attacks pose a serious concern for AI model providers. In this work, we present a novel attack targeting wireless devices equipped with AI hardware accelerators. The attack unfolds in two phases. In the first phase, the victim’s device is compromised with a hardware Trojan (HT) designed to covertly leak model weights through a hidden communication channel, without the victim realizing it. In the second phase, the adversary uses a nearby wireless device to intercept the victim’s transmission frames during normal operation and incrementally reconstruct the complete weight matrix. The proposed attack is agnostic to both the AI model architecture and the hardware accelerator used. We validate our approach through a hardware-based demonstration involving five diverse AI models of varying types and sizes. We detail the design of the HT and the covert channel, highlighting their stealthy nature. Additionally, we analyze the impact of bit error rates (BERs) on the reception and propose an error mitigation technique. The effectiveness of the attack is evaluated based on the accuracy of the reconstructed models with stolen weights and the time required to extract them. Finally, we explore potential defense mechanisms.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 7","pages":"2098-2111"},"PeriodicalIF":3.2,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148512332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Groupwise Add--Multiply--Shift--Accumulate Datapath for Efficient DNN Accelerators 高效DNN加速器的分组加-乘-移-累加数据路径

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-07-01 Epub Date: 2026-03-08 DOI: 10.1109/TVLSI.2026.3689624

Zhiwang Huo;Wenzhe Zhao;Yuanchang Gong;Tian Xia;Zheng Wang;Pengju Ren

{"title":"A Groupwise Add--Multiply--Shift--Accumulate Datapath for Efficient DNN Accelerators","authors":"Zhiwang Huo;Wenzhe Zhao;Yuanchang Gong;Tian Xia;Zheng Wang;Pengju Ren","doi":"10.1109/TVLSI.2026.3689624","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3689624","url":null,"abstract":"Multiply–accumulate(MAC) units account for a large fraction of the power and area in modern deep neural network (DNN) accelerators. Although low-bitwidth quantization reduces hardware overhead, the high cost of multipliers remains a fundamental bottleneck in modern accelerator datapaths. This article proposes add–multiply–shift–accumulate (AMC), a groupwise arithmetic datapath that reduces multiplier count by sharing base multiplications across groups of neighboring weights and generating residual products using lightweight shift operation. To support efficient deployment, we design a compact residual encoding and buffer organization that allows AMC arrays to be constructed with minimal decoding and control overheads. While AMC can be directly applied to existing quantized models, we further introduce a lightweight residual-aware fine-tuning (RAF) procedure to increase AMC compatibility. We implement AMC-based accelerators in SystemVerilog and synthesize them in TSMC 28-nm CMOS technology across operating frequencies from 500 MHz to 1 GHz. At the compute unit level, AMC reduces arithmetic area by 39.5%–62.8% and dynamic power by 32.2%–60.3% compared with optimized baseline multipliers. When integrated into CNN and Vision Transformer accelerators, AMC achieves <inline-formula> <tex-math>$1.34times $ </tex-math></inline-formula>–<inline-formula> <tex-math>$18.90times $ </tex-math></inline-formula> higher area efficiency and up to <inline-formula> <tex-math>$10.16times $ </tex-math></inline-formula> higher energy efficiency than prior designs while preserving baseline inference accuracy.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 7","pages":"2112-2125"},"PeriodicalIF":3.2,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148512334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Low-Power, High-Throughput Multimode FFT Processor Incorporating the ASPC Algorithm 基于ASPC算法的低功耗、高吞吐量多模FFT处理器

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-07-01 Epub Date: 2026-03-08 DOI: 10.1109/TVLSI.2026.3688149

Kuang-Hao Lin;Tzu-Yi Tseng

{"title":"A Low-Power, High-Throughput Multimode FFT Processor Incorporating the ASPC Algorithm","authors":"Kuang-Hao Lin;Tzu-Yi Tseng","doi":"10.1109/TVLSI.2026.3688149","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3688149","url":null,"abstract":"In digital signal processing (DSP), the fast Fourier transform (FFT) serves as a core algorithm for converting signals from the time domain to the frequency domain and is widely applied in fields such as communication systems, biomedical signal processing, and artificial intelligence (AI). However, as application demands become increasingly diverse, FFT processor design must not only support various computation lengths but also achieve an optimal balance among computational speed, power consumption, and hardware resource utilization. This article proposes a low-power, high-throughput FFT processor with dedicated hardware architectures for both field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) platforms, supporting 16/32/64/128/256-point FFT computations. The processor incorporates the proposed adaptive stage parameter configuration (ASPC) algorithm, which enables rapid hardware reconfiguration and dynamic activation of computational modules based on specific application requirements and resource constraints. In addition, the design integrates coordinate rotation digital computer (CORDIC) and clock-gating techniques to further reduce the use of multipliers and overall power consumption. Experimental results show that, for 256-point computation, the proposed FFT processor uses only 14 040 LUTs and 27 566 FFs in the FPGA flow, completely avoiding the use of costly DSP resources. In the ASIC flow, the normalized throughput per area of the processor was 1.70 GS/s, completing 35.25 FFTs per unit of energy. Compared to existing studies, the proposed FFT processor achieves up to a 51.78% improvement in throughput and a 5% improvement in energy efficiency while attaining a signal-to-quantization noise ratio (SQNR) of 49.26 dB, indicating superior overall performance and design quality.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 7","pages":"2201-2212"},"PeriodicalIF":3.2,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148515112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Single-Input Dual-Output Wireless Power Transfer System With Load-Optimized Matching Network 基于负载优化匹配网络的单输入双输出无线电力传输系统

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-07-01 Epub Date: 2026-04-29 DOI: 10.1109/TVLSI.2026.3686340

Sungmin Shin;Seongbin Kwon;Geonwoo Baek;Gyeongho Namgoong;Franklin Bien

{"title":"A Single-Input Dual-Output Wireless Power Transfer System With Load-Optimized Matching Network","authors":"Sungmin Shin;Seongbin Kwon;Geonwoo Baek;Gyeongho Namgoong;Franklin Bien","doi":"10.1109/TVLSI.2026.3686340","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3686340","url":null,"abstract":"This article presents a single-input–dual-output (SIDO) wireless power transfer (WPT) system that maintains high link efficiency across both heavy and light load conditions. Conventional SIDO architectures employ a fixed matching network, which leads to significant efficiency degradation when the load changes. To address this limitation, the proposed system classifies the two outputs into heavy-load and light-load domains and employs dedicated matching networks optimized for each operating condition, thereby maximizing link efficiency during charging of either load. To minimize the power overhead of mode switching while enabling single-stage AC–DC regulation, a charging-phase controller, a full/half-window mode controller, and an adaptive window generator are employed. Furthermore, an active rectifier with a slowdown unit cell (SUC)-based on/off controller (SOOC) is proposed to improve power conversion efficiency (PCE). In addition, an early turn-on switching (ETS) is implemented to achieve higher PCE compared to conventional zero-voltage switching (ZVS). Fabricated in a 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m BCD process, the system is implemented as two chips, a standalone rectifier for accurate PCE measurement and a SIDO integrating the same rectifier. The SIDO demonstrates stable full/half-window operation without multiple pulsing. Measured link efficiency reaches 94.4% at 3 mA and 92.7% at 30 mA at a coupling coefficient k = 0.2, confirming the effectiveness of the load-optimized matching. The rectifier achieves 94.5% peak PCE and maintains above 92.3% PCE across a 2.5–5.0 V input range.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 7","pages":"2247-2259"},"PeriodicalIF":3.2,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148515114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Energy-Efficient Logarithmic Floating-Point Multipliers Using Truncation-Based Error Compensation for Fault-Tolerant Applications 基于截断误差补偿的高效对数浮点乘法器容错应用

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-07-01 Epub Date: 2026-03-05 DOI: 10.1109/TVLSI.2026.3689058

Zheng Li;Baining Wu;Jilong Zhang;Chao Chen;Yongliang Zhang;Yan Li;Xiaoyang Zeng

{"title":"Energy-Efficient Logarithmic Floating-Point Multipliers Using Truncation-Based Error Compensation for Fault-Tolerant Applications","authors":"Zheng Li;Baining Wu;Jilong Zhang;Chao Chen;Yongliang Zhang;Yan Li;Xiaoyang Zeng","doi":"10.1109/TVLSI.2026.3689058","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3689058","url":null,"abstract":"The growing demand for energy-efficient computing in resource-constrained devices necessitates approximate arithmetic solutions that balance accuracy and hardware cost. This article presents a family of logarithmic truncation-based approximate multipliers (LTAMs) for floating-point (FP) operations, including two hardware cost-optimized architectures (LTAM1 and LTAM2) and an accuracy-focused lookup table (LUT)-based design (LTAM-LUT). All designs effectively address the systematic negative bias inherent in classical logarithmic multipliers through advanced error compensation methods. Based on a comprehensive analysis, a 6-bit mantissa truncation is identified as the optimal configuration. Under the 6-bit configuration, LTAM1-6 achieves 52.9% area and 77.6% power-delay product (PDP) reduction compared to conventional logarithmic approximate multipliers, while LTAM2-6 provides 45.1% area and 70.4% PDP reduction. LTAM-LUT achieves 56.4% accuracy improvement over conventional logarithmic approximate multipliers with a mean relative error distance (MRED) of 1.68%, the lowest among all compared designs. These hardware efficiency gains are also validated across diverse application domains. In HDR tone mapping, LTAM-LUT achieves up to 7.0 dB higher peak signal-to-noise ratio (PSNR) than conventional designs, while LTAM1-6 and LTAM2-6 provide 1.1- and 4.6-dB improvements, respectively. For single-image super-resolution (SISR) on DIV2K (<inline-formula> <tex-math>$times 4$ </tex-math></inline-formula> scale), LTAM-LUT preserves reconstruction quality nearly identical to exact arithmetic on HAT (29.73 dB) and achieves up to 2.3 dB higher PSNR than conventional logarithmic multipliers on EDSR, while LTAM1-6 and LTAM2-6 consistently outperform prior approximate designs across all tested architectures, demonstrating superior accuracy–efficiency tradeoffs for error-tolerant applications.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 7","pages":"2151-2164"},"PeriodicalIF":3.2,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148511471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

TriCIM: A General CIM-Capacity-Aware Framework for Optimizing Model, Layer, and Tile-Stationary Dataflows in CIM Accelerators 一个通用的CIM容量感知框架，用于优化CIM加速器中的模型、层和平块固定数据流

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-07-01 Epub Date: 2026-03-07 DOI: 10.1109/TVLSI.2026.3688907

Jin Wang;Yufu Zhang;Longyang Lin

{"title":"TriCIM: A General CIM-Capacity-Aware Framework for Optimizing Model, Layer, and Tile-Stationary Dataflows in CIM Accelerators","authors":"Jin Wang;Yufu Zhang;Longyang Lin","doi":"10.1109/TVLSI.2026.3688907","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3688907","url":null,"abstract":"Compute-in-memory (CIM) has emerged as a promising paradigm for accelerating neural networks (NNs), offering high parallelism and superior energy efficiency. To fully leverage the potential of CIM accelerators for deploying NNs, it is essential to carefully optimize their mapping dataflows, which determine how computations and data are scheduled across CIM resources over space and time. However, the diversity of CIM architectures, with their varying hardware parameters and mapping constraints, makes it challenging to develop a unified framework that efficiently optimizes dataflows across different CIM systems. Most existing CIM dataflow frameworks are tailored to a limited range of architectures or dataflow types, and often neglect CIM-specific features such as weight-update scheduling, which limits their effectiveness and generality. In this work, we propose TriCIM, a general dataflow optimization framework designed to adapt to diverse CIM architectures. We begin by introducing a CIM-capacity-aware formulation that classifies the CIM dataflow space into three distinct regions, model-stationary, layer-stationary, and tile-stationary, based on the available CIM capacity and the model size. For each dataflow region, we identify specific bottlenecks and propose tailored optimization strategies, including load balancing, layer grouping, weight-update scheduling, tiling, and inter-tile ordering, to address region-specific bottlenecks and enhance dataflow efficiency. Our evaluation across various CIM accelerators and representative NN models demonstrates that TriCIM consistently finds optimal dataflows, achieving <inline-formula> <tex-math>$1.1times $ </tex-math></inline-formula> to <inline-formula> <tex-math>$13.2times $ </tex-math></inline-formula> runtime speedup compared to state-of-the-art frameworks.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 7","pages":"2187-2200"},"PeriodicalIF":3.2,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148512329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Memory-Optimized Block Compression for High-Speed Memory Testing 内存优化块压缩高速内存测试

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-07-01 Epub Date: 2026-04-28 DOI: 10.1109/TVLSI.2026.3686478

Gyeonggyu Park;Duyeon Won;Juyong Lee;Youngki Moon;Sungho Kang

{"title":"Memory-Optimized Block Compression for High-Speed Memory Testing","authors":"Gyeonggyu Park;Duyeon Won;Juyong Lee;Youngki Moon;Sungho Kang","doi":"10.1109/TVLSI.2026.3686478","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3686478","url":null,"abstract":"In memory testing, test vectors are generated by automatic test equipment (ATE) during testing. To detect diverse faults introduced in modern memories, flexibility in implementing diverse test conditions is required. However, the complex operations for test vector generation during testing make it challenging to achieve high-speed testing and high flexibility simultaneously. In vector memory (VM)-based testing, complex operations are mitigated because test vectors are pre-generated and applied directly to the memory under test (MUT) during testing. However, test vector compression is necessary to address the limited capacity and data-loading speed of the VM. Although conventional code-based compression methods for logic testing are applicable to memory test vectors, low compression ratios are observed due to fundamental differences between logic and memory test vectors. To achieve both high-speed testing and high flexibility, a memory-optimized block compression (MOBC) is proposed. Each field, comprising inputs with the same functional role, is compressed independently by exploiting fundamental characteristics of memory test vectors (e.g., field-specific characteristics and timing constraints). On average, a 36.3% higher compression ratio is achieved compared to conventional compression methods. In addition, the MOBC decoder achieves a higher operating frequency than conventional test vector generators, regardless of the test conditions.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 7","pages":"2284-2295"},"PeriodicalIF":3.2,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148514576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hardware-Efficient Low-Distortion Sinusoidal Signal Generator Using FPGA-Based Dual-DAC Digital Predistortion 基于fpga的双dac数字预失真硬件高效低失真正弦信号发生器

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-07-01 Epub Date: 2026-04-20 DOI: 10.1109/TVLSI.2026.3683742

Keno Sato;Takayuki Nakatani;Toshiyuki Okamoto;Takashi Ishida;Tamotsu Ichikawa;Shogo Katayama;Daisuke Iimori;Misaki Takagi;Yujie Zhao;Shuhei Yamamoto;Jianglin Wei;Anna Kuwana;Kentaroh Katoh;Kazumi Hatayama;Haruo Kobayashi

{"title":"Hardware-Efficient Low-Distortion Sinusoidal Signal Generator Using FPGA-Based Dual-DAC Digital Predistortion","authors":"Keno Sato;Takayuki Nakatani;Toshiyuki Okamoto;Takashi Ishida;Tamotsu Ichikawa;Shogo Katayama;Daisuke Iimori;Misaki Takagi;Yujie Zhao;Shuhei Yamamoto;Jianglin Wei;Anna Kuwana;Kentaroh Katoh;Kazumi Hatayama;Haruo Kobayashi","doi":"10.1109/TVLSI.2026.3683742","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3683742","url":null,"abstract":"This article presents hardware-efficient harmonics cancellation techniques using digital predistortion (DPD) for low-distortion sinusoidal signal generation, targeted for the dynamic characteristic testing of high-resolution 14-bit and 16-bit 1 MS/s analog-to-digital converters (ADCs) in VLSI testing environments. For 14-bit ADC testing, a single 16-bit digital-to-analog converter (DAC) with a simplified DPD circuit is demonstrated to achieve a second-order harmonic distortion (HD2) level of −92 dBc. For 16-bit ADC testing, where higher resolution is required, we propose a novel dual-DAC architecture utilizing a dual-range synthesis method to enhance effective resolution and suppress harmonics up to the fifth-order (HD2–HD5). Furthermore, to minimize the hardware overhead in practical implementations, we introduce optimized field-programmable gate array (FPGA) design strategies, including time-division multiplexing (TDM) and compressed sine look-up tables (LUTs), achieving a 96.8% reduction in memory usage. The parameters are extracted via a single-step, deterministic calibration flow, ensuring high testing throughput without iterative optimization. Experimental results show HD2–HD5 levels down to −120 dBc, providing a hardware-efficient solution for high-precision built-out self-test (BOST) and future system-on-chip (SoC) integration.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 7","pages":"2238-2246"},"PeriodicalIF":3.2,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148514586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Current-Steering DAC With a Complementary Structured Charge-Pump-Based Voltage-Limited Driver for Code-Dependent Error Suppression 电流导向DAC与互补结构电荷泵限压驱动的码相关错误抑制

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-07-01 Epub Date: 2026-04-29 DOI: 10.1109/TVLSI.2026.3685243

Tianyu Yu;Biwen Shi;Wei Zhang;Deng Luo;Xin Zhang;Ming Tao;Jianjun Chen;Yaqing Chi;Guofang Yu;Dongxun Li;Bin Liang

引用次数: 0

A Bit-Level Loosely Coupled Spiking Neural Network Accelerator With Fast Inference and Hybrid Early Termination 具有快速推理和混合提前终止的位级松耦合尖峰神经网络加速器

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-07-01 Epub Date: 2026-03-07 DOI: 10.1109/TVLSI.2026.3688394

Junchuan Gu;Yiwen Gu;Xinran Li;Haibin Shen;Kejie Huang

引用次数: 0