Toward High-Performance Network Coding: FPGA Acceleration With Bounded-Value Generators

IF 3.1 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-06-02 DOI:10.1109/TVLSI.2025.3572517

Jiaxin Qing;Philip H. W. Leong;Kin-Hong Lee;Raymond W. Yeung

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引用次数: 0

Abstract

The network coding enhances performance in network communications and distributed storage by increasing throughput and robustness while reducing latency. Batched sparse (BATS) codes are a class of capacity-achieving network codes, but their practical applications are hindered by their structure, computational intensity, and power demands of finite field (FF) operations. Most literature focuses on algorithmic-level techniques to improve the coding efficiency. Optimization with an algorithm/hardware co-designing approach has long been neglected. Leveraging the unique structure of BATS codes, we first present cyclic-shift BATS (CS-BATS), a hardware-friendly variant. Next, we propose a simple but effective bounded-value (BV) generator, to reduce the size of a finite field multiplier by up to 70%. Finally, we report on a scalable and resource-efficient field-programmable gate array (FPGA)-based network coding accelerator that achieves a throughput of 27 Gb/s, a speedup of more than 300 over software.

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迈向高性能网络编码：FPGA加速与有界值生成器

网络编码通过增加吞吐量和鲁棒性来提高网络通信和分布式存储的性能，同时减少延迟。批处理稀疏码（Batched sparse code， BATS）是一类容量实现型网络码，但其结构、计算强度和有限域（finite field， FF）运算的功率需求等限制了其实际应用。大多数文献关注于算法级技术来提高编码效率。长期以来，算法/硬件协同设计方法的优化一直被忽视。利用BATS代码的独特结构，我们首先提出了一种硬件友好型的循环移位BATS （CS-BATS）。接下来，我们提出了一个简单但有效的有界值（BV）生成器，以减少有限域乘法器的大小高达70%。最后，我们报告了一种可扩展且资源高效的基于现场可编程门阵列（FPGA）的网络编码加速器，其吞吐量达到27 Gb/s，比软件加速300以上。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.