IEEE Transactions on Very Large Scale Integration (VLSI) Systems最新文献

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information 电气和电子工程师学会超大规模集成 (VLSI) 系统学会论文集信息

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-10-25 DOI: 10.1109/TVLSI.2024.3474954

引用次数: 0

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information IEEE 超大规模集成 (VLSI) 系统论文集出版信息

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-10-25 DOI: 10.1109/TVLSI.2024.3474952

引用次数: 0

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information IEEE 超大规模集成 (VLSI) 系统论文集出版信息

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-09-26 DOI: 10.1109/TVLSI.2024.3457191

引用次数: 0

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information 电气和电子工程师学会超大规模集成 (VLSI) 系统学会论文集信息

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-09-26 DOI: 10.1109/TVLSI.2024.3457193

引用次数: 0

The Error Analysis of Bit Weight Self-Calibration Methods for High-Resolution SAR ADCs 高分辨率 SAR ADC 比特权重自校准方法的误差分析

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-09-19 DOI: 10.1109/TVLSI.2024.3458071

Yanhang Chen;Siji Huang;Qifeng Huang;Yifei Fan;Jie Yuan

{"title":"The Error Analysis of Bit Weight Self-Calibration Methods for High-Resolution SAR ADCs","authors":"Yanhang Chen;Siji Huang;Qifeng Huang;Yifei Fan;Jie Yuan","doi":"10.1109/TVLSI.2024.3458071","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3458071","url":null,"abstract":"High-resolution successive approximation register (SAR) analog-to-digital converters (ADCs) commonly need to calibrate their bit weights. Due to the nonidealities of the calibration circuits, the calibrated bit weights carry errors. This error could propagate during the calibration procedure. Due to the high precision requirement of these ADCs, such residue error commonly becomes the signal-to-noise-and-distortion ratio (SNDR) bottleneck of the overall ADC. This article presents an analysis of the residue error from bit weight self-calibration methods of high-resolution SAR ADCs. The major sources contributing to this error and the error reduction methods are quantitively analyzed. A statistical analysis of the noise-induced random error is developed. Our statistical model finds that the noise-induced random error follows the chi-square distribution. In practice, this random error is commonly reduced by repetitively measuring and averaging the calibrated bit weights. Our statistical model quantifies this bit weight error and leads to a clearer understanding of the error mechanism and design trade-offs. Following our chi-square model, the SNDR degradation due to the circuit noise during the calibration can be easily estimated without going through the time-consuming traditional transistor-level design and simulation process. The required repetition time can also be calculated. The bit-weight error models derived in this article are verified with measurement on a 16-bit SAR ADC design in a 180-nm CMOS process. Results from our model match both simulations and measurements well.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

MCAIMem: A Mixed SRAM and eDRAM Cell for Area and Energy-Efficient On-Chip AI Memory MCAIMem：用于面积和能效高的片上人工智能存储器的混合 SRAM 和 eDRAM 单元

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-09-18 DOI: 10.1109/TVLSI.2024.3439231

Duy-Thanh Nguyen;Abhiroop Bhattacharjee;Abhishek Moitra;Priyadarshini Panda

{"title":"MCAIMem: A Mixed SRAM and eDRAM Cell for Area and Energy-Efficient On-Chip AI Memory","authors":"Duy-Thanh Nguyen;Abhiroop Bhattacharjee;Abhishek Moitra;Priyadarshini Panda","doi":"10.1109/TVLSI.2024.3439231","DOIUrl":"10.1109/TVLSI.2024.3439231","url":null,"abstract":"AI chips commonly employ SRAM memory as buffers for their reliability and speed, which contribute to high performance. However, SRAM is expensive and demands significant area and energy consumption. Previous studies have explored replacing SRAM with emerging technologies, such as nonvolatile memory, which offers fast read memory access and a small cell area. Despite these advantages, nonvolatile memory’s slow write memory access and high write energy consumption prevent it from surpassing SRAM performance in AI applications with extensive memory access requirements. Some research has also investigated embedded dynamic random access memory (eDRAM) as an area-efficient on-chip memory with similar access times as SRAM. Still, refresh power remains a concern, leaving the trade-off among performance, area, and power consumption unresolved. To address this issue, this article presents a novel mixed CMOS cell memory design that balances performance, area, and energy efficiency for AI memory by combining SRAM and eDRAM cells. We consider the proportion ratio of one SRAM and seven eDRAM cells in the memory to achieve area reduction using mixed CMOS cell memory. In addition, we capitalize on the characteristics of deep neural network (DNN) data representation and integrate asymmetric eDRAM cells to lower energy consumption. To validate our proposed MCAIMem solution, we conduct extensive simulations and benchmarking against traditional SRAM. Our results demonstrate that the MCAIMem significantly outperforms these alternatives in terms of area and energy efficiency. Specifically, our MCAIMem can reduce the area by 48% and energy consumption by \u0000<inline-formula> <tex-math>$3.4times $ </tex-math></inline-formula>\u0000 compared with SRAM designs, without incurring any accuracy loss.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142266248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Marmotini: A Weight Density Adaptation Architecture With Hybrid Compression Method for Spiking Neural Network Marmotini：采用混合压缩方法的尖峰神经网络权重密度自适应架构

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-09-18 DOI: 10.1109/tvlsi.2024.3453897

Zilin Wang, Yi Zhong, Zehong Ou, Youming Yang, Shuo Feng, Guang Chen, Xiaoxin Cui, Song Jia, Yuan Wang

引用次数: 0

A 22-nm 264-GOPS/mm$^{2}$ 6T SRAM and Proportional Current Compute Cell-Based Computing-in-Memory Macro for CNNs 用于 CNN 的 22 纳米 264-GOPS/mm$^{2}$ 6T SRAM 和基于比例电流计算单元的内存计算宏

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-09-18 DOI: 10.1109/tvlsi.2024.3446045

Feiran Liu, Anran Yin, Chen Xue, Bo Wang, Zhongyuan Feng, Han Liu, Xiang Li, Hui Gao, Tianzhu Xiong, Xin Si

引用次数: 0

An Interpolation-Free Fractional Motion Estimation Algorithm and Hardware Implementation for VVC 用于 VVC 的无插值分数运动估计算法和硬件实现

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-09-17 DOI: 10.1109/tvlsi.2024.3455374

Shushi Chen, Leilei Huang, Zhao Zan, Xiaoyang Zeng, Yibo Fan

引用次数: 0

55–100-GHz Enhanced Gilbert Cell Mixer Design in 22-nm FDSOI CMOS 采用 22 纳米 FDSOI CMOS 的 55-100-GHz 增强型吉尔伯特单元混频器设计

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-09-17 DOI: 10.1109/tvlsi.2024.3454350

Kimi Jokiniemi, Kaisa Ryynänen, Joni Vähä, Elmo Kankkunen, Kari Stadius, Jussi Ryynänen

引用次数: 0