IEEE Transactions on Very Large Scale Integration (VLSI) Systems最新文献

Corrections to “Enhancing Memory BIST With an Optimized RTL-BIST IP Core: A Low-Power, High-Fault-Coverage Approach” 更正“使用优化的RTL-BIST IP核增强内存BIST：低功耗，高故障覆盖方法”

IF 3.1 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-09-26 DOI: 10.1109/TVLSI.2025.3600857

Ming-Yi Lin;Wei-Kuan Chiang;Chin-Hung Wang

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IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information 超大规模集成电路（VLSI）系统学报

IF 3.1 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-09-26 DOI: 10.1109/TVLSI.2025.3609598

引用次数: 0

ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits 基于sram的模拟CiM电路的建模与推理精度分析

IF 3.1 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-09-05 DOI: 10.1109/TVLSI.2025.3605286

Wenlun Zhang;Shimpei Ando;Yung-Chin Chen;Kentaro Yoshioka

{"title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","authors":"Wenlun Zhang;Shimpei Ando;Yung-Chin Chen;Kentaro Yoshioka","doi":"10.1109/TVLSI.2025.3605286","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3605286","url":null,"abstract":"Static random-access memory (SRAM)-based analog compute-in-memory (ACiM) demonstrates promising energy efficiency for deep neural network (DNN) processing. Nevertheless, efforts to optimize efficiency frequently compromise accuracy, and this trade-off remains insufficiently studied due to the difficulty of performing full-system validation. Specifically, existing simulation tools rarely target SRAM-based ACiM and exhibit inconsistent accuracy predictions, highlighting the need for a standardized, SRAM compute-in-memory (CiM) circuit-aware evaluation methodology. This article presents ASiM, a simulation framework for evaluating inference accuracy in SRAM-based ACiM systems. ASiM captures critical effects in SRAM-based analog compute in memory systems, such as analog-to-digital converter (ADC) quantization, bit-parallel encoding, and analog noise, which must be modeled with high fidelity due to their distinct behavior in charge-domain architectures compared to other memory technologies. ASiM supports a wide range of modern DNN workloads, including CNN and Transformer-based models such as ViT, and scales to large-scale tasks like ImageNet classification. Our results indicate that bit-parallel encoding can improve energy efficiency with only modest accuracy degradation; however, even 1 LSB of analog noise can significantly impair inference performance, particularly in complex tasks such as ImageNet. To address this, we explore hybrid analog-digital execution and majority voting schemes, both of which enhance robustness without negating energy savings. ASiM bridges the gap between hardware design and inference performance, offering actionable insights for energy-efficient, high-accuracy ACiM deployment. The code is available at <uri>https://github.com/Keio-CSG/ASiM</uri>","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 10","pages":"2838-2851"},"PeriodicalIF":3.1,"publicationDate":"2025-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145141714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Guest Editorial: Selected Papers From IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2024 嘉宾评论：IEEE计算机学会超大规模集成电路（ISVLSI）年度研讨会论文选集

IF 3.1 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-08-26 DOI: 10.1109/TVLSI.2025.3593728

Himanshu Thapliyal;Jürgen Becker;Garrett S. Rose;Tosiron Adegbija;Selçuk Köse

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IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information IEEE超大规模集成电路（VLSI）系统学报

IF 3.1 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-08-26 DOI: 10.1109/TVLSI.2025.3598542

引用次数: 0

Corrections to “An Efficient Two-Stage Pipelined Compute-in-Memory Macro for Accelerating Transformer Feed-Forward Networks” 对“用于加速变压器前馈网络的高效两阶段流水线内存计算宏”的修正

IF 3.1 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-08-26 DOI: 10.1109/TVLSI.2025.3582145

Heng Zhang;Wenhe Yin;Sunan He;Yuan Du;Li Du

引用次数: 0

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information 超大规模集成电路（VLSI）系统学报

IF 3.1 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-08-26 DOI: 10.1109/TVLSI.2025.3598544

引用次数: 0

FASE: An FPGA-Based Accelerator for Lightweight Sample Entropy With Monte Carlo Sampling FASE：一种基于fpga的蒙特卡罗采样轻量级样本熵加速器

IF 3.1 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-08-06 DOI: 10.1109/TVLSI.2025.3593020

Jiayu Liu;Yuanhang Li;Zhengyang Huang;Chao Chen;Ruiqi Chen;Bruno da Silva

{"title":"FASE: An FPGA-Based Accelerator for Lightweight Sample Entropy With Monte Carlo Sampling","authors":"Jiayu Liu;Yuanhang Li;Zhengyang Huang;Chao Chen;Ruiqi Chen;Bruno da Silva","doi":"10.1109/TVLSI.2025.3593020","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3593020","url":null,"abstract":"Sample entropy (SampEn) is an algorithm within information entropy that enables effective analysis of biological signals. Due to the need for extensive similarity matching operations, the SampEn calculation process is time-consuming. Although a series of fast SampEn algorithms have been proposed, they remain time-intensive when processing large data volumes. Additionally, previous field-programmable gate array (FPGA)-based hardware accelerators designed for SampEn suffer from architectural design limitations, consuming substantial on-chip memory resources and operating at low frequencies. In this article, we propose FASE, an FPGA-based accelerator for lightweight sample entropy (LW-SampEn) with Monte Carlo (MC) sampling. The FASE design comprises two main parts: algorithm and hardware optimizations. On the algorithmic side, we introduce MC sampling into the merge-sort-based LW-SampEn algorithm, named MCLW-SampEn. MCLW-SampEn effectively reduces the computation load for large data volumes while maintaining algorithmic accuracy. For hardware, we first design efficient sorting and allocation modules to address boundary localization and load imbalance issues in previous accelerator designs. Then, we replicate the computation across the main phases to enable parallel processing. Finally, we deploy the design on the Pynq-Z2 board for validation. Experimental results show that the proposed MCLW-SampEn algorithm achieves an average speed up of <inline-formula> <tex-math>$3times $ </tex-math></inline-formula> over the LW-SampEn algorithm, with accuracy losses kept within 0.5%. Compared to state-of-the-art (SOTA) designs, FASE achieves an average speed up of <inline-formula> <tex-math>$12.8times $ </tex-math></inline-formula> while reducing power consumption by 89.3%. Ablation studies indicate that, for the same algorithm, FASE offers a <inline-formula> <tex-math>$7.4times $ </tex-math></inline-formula> speedup over related FPGA designs.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 10","pages":"2883-2896"},"PeriodicalIF":3.1,"publicationDate":"2025-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145141710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Cross-Layer Approximate Design of Low-Power Fractional Motion Estimation Accelerators for VVC VVC低功耗分数阶运动估计加速器的跨层近似设计

IF 3.1 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-08-06 DOI: 10.1109/TVLSI.2025.3589984

Rafael da Silva;Pedro T. L. Pereira;Mateus Grellert;Ricardo Reis

{"title":"Cross-Layer Approximate Design of Low-Power Fractional Motion Estimation Accelerators for VVC","authors":"Rafael da Silva;Pedro T. L. Pereira;Mateus Grellert;Ricardo Reis","doi":"10.1109/TVLSI.2025.3589984","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3589984","url":null,"abstract":"The versatile video coding (VVC) standard introduces several innovative tools designed to enhance coding efficiency compared with its predecessors. One example is the adoption of an alternative filter for fractional motion estimation (FME) that is part of the adaptive motion vector resolution (AMVR) extension. While this allows a more precise motion representation, it also incurs more complexity for hardware implementations that aim at supporting most of VVC features. This work introduces a low-power hardware architecture accelerator specifically designed for FME with support for the AMVR extension of VVC. The proposed solution enables a systematic exploration of the design space of cross-layer approximate computing by combining approximations at both the operator and algorithm levels. This is achieved through the design of two novel architectures (<italic>2TAxA/4T</i> and <italic>2TAxA/2TAxA</i>) alongside a newly proposed approximate filter applicable to both regular and alternative interpolation modes. Furthermore, we evaluate eight different approximate adder (AA) topologies to optimize power–quality tradeoffs. Experimental results demonstrate that for a complete FME multifilter interpolation unit (MIU) and maintaining an image quality threshold of <inline-formula> <tex-math>$text {SSIM} geq 0.88$ </tex-math></inline-formula>, our method achieves up to 72% power savings and 59.64% area savings.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 9","pages":"2415-2423"},"PeriodicalIF":3.1,"publicationDate":"2025-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information IEEE超大规模集成电路（VLSI）系统学报

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-07-25 DOI: 10.1109/TVLSI.2025.3587928

引用次数: 0