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IEEE Transactions on Very Large Scale Integration (VLSI) Systems最新文献

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Sophon: A Time-Repeatable and Low-Latency Architecture for Embedded Real-Time Systems Based on RISC-V Sophon：基于 RISC-V 的可重复时间和低延迟嵌入式实时系统架构
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-09-11 DOI: 10.1109/tvlsi.2024.3447279
Zhe Huang, Xingyao Chen, Feng Gao, Ruige Li, Xiguang Wu, Fan Zhang
{"title":"Sophon: A Time-Repeatable and Low-Latency Architecture for Embedded Real-Time Systems Based on RISC-V","authors":"Zhe Huang, Xingyao Chen, Feng Gao, Ruige Li, Xiguang Wu, Fan Zhang","doi":"10.1109/tvlsi.2024.3447279","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3447279","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142194447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
CR-DRAM: Improving DRAM Refresh Energy Efficiency With Inter-Subarray Charge Recycling CR-DRAM：利用子阵列间电荷回收提高 DRAM 刷新能效
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-09-11 DOI: 10.1109/tvlsi.2024.3445631
Haitao Du, Hairui Zhu, Song Chen, Yi Kang
{"title":"CR-DRAM: Improving DRAM Refresh Energy Efficiency With Inter-Subarray Charge Recycling","authors":"Haitao Du, Hairui Zhu, Song Chen, Yi Kang","doi":"10.1109/tvlsi.2024.3445631","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3445631","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142225011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Novel TriNet Architecture for Enhanced Analog IC Design Automation 用于增强模拟集成电路设计自动化的新型 TriNet 架构
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-09-10 DOI: 10.1109/tvlsi.2024.3452032
Arunkumar P Chavan, Shrish Shrinath Vaidya, Sanket M. Mantrashetti, Abhishek Gurunath Dastikopp, Kishan S. Murthy, H. V. Ravish Aradhya, Prakash Pawar
{"title":"A Novel TriNet Architecture for Enhanced Analog IC Design Automation","authors":"Arunkumar P Chavan, Shrish Shrinath Vaidya, Sanket M. Mantrashetti, Abhishek Gurunath Dastikopp, Kishan S. Murthy, H. V. Ravish Aradhya, Prakash Pawar","doi":"10.1109/tvlsi.2024.3452032","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3452032","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142194448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Two-Channel Interleaved ADC With Fast-Converging Foreground Time Calibration and Comparison-Based Control Logic 具有快速转换前景时间校准和基于比较的控制逻辑的双通道交错 ADC
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-09-09 DOI: 10.1109/tvlsi.2024.3449293
Xiang Yan, Kefan Qin, Xinyue Zheng, Weibo Hu, Wei Ma, Haitao Cui
{"title":"A Two-Channel Interleaved ADC With Fast-Converging Foreground Time Calibration and Comparison-Based Control Logic","authors":"Xiang Yan, Kefan Qin, Xinyue Zheng, Weibo Hu, Wei Ma, Haitao Cui","doi":"10.1109/tvlsi.2024.3449293","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3449293","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142194450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multiobjective Optimization of Class-F Oscillators F 类振荡器的多目标优化
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-09-05 DOI: 10.1109/tvlsi.2024.3449567
Zhan Qu, Zhenjiao Chen, Xingqiang Shi, Ya Zhao, Guohe Zhang, Feng Liang
{"title":"Multiobjective Optimization of Class-F Oscillators","authors":"Zhan Qu, Zhenjiao Chen, Xingqiang Shi, Ya Zhao, Guohe Zhang, Feng Liang","doi":"10.1109/tvlsi.2024.3449567","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3449567","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142225029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Post-Bond ILV Test Method in Monolithic 3-D ICs 单片三维集成电路中的粘接后 ILV 测试方法
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-09-05 DOI: 10.1109/tvlsi.2024.3450452
Xu Fang, Xiaofeng Zhao
{"title":"A Post-Bond ILV Test Method in Monolithic 3-D ICs","authors":"Xu Fang, Xiaofeng Zhao","doi":"10.1109/tvlsi.2024.3450452","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3450452","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142194452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Double-Data-Rate Ripple Counter With Calibration Circuits for Correlated Multiple Sampling in CMOS Image Sensors 带校准电路的双数据率纹波计数器，用于 CMOS 图像传感器中的相关多重采样
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-09-04 DOI: 10.1109/tvlsi.2024.3449320
Wanbin Zha, Jiangtao Xu, Kaiming Nie, Zhiyuan Gao
{"title":"A Double-Data-Rate Ripple Counter With Calibration Circuits for Correlated Multiple Sampling in CMOS Image Sensors","authors":"Wanbin Zha, Jiangtao Xu, Kaiming Nie, Zhiyuan Gao","doi":"10.1109/tvlsi.2024.3449320","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3449320","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142194451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Unveiling the True Power of the Latched Ring Oscillator for a Unified PUF and TRNG Architecture 揭示用于统一 PUF 和 TRNG 架构的锁相环振荡器的真正威力
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-09-04 DOI: 10.1109/tvlsi.2024.3448503
Riccardo Della Sala, Davide Bellizia, Giuseppe Scotti
{"title":"Unveiling the True Power of the Latched Ring Oscillator for a Unified PUF and TRNG Architecture","authors":"Riccardo Della Sala, Davide Bellizia, Giuseppe Scotti","doi":"10.1109/tvlsi.2024.3448503","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3448503","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142194476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
ReAdapt-II: Energy-Quality Optimizations for VLSI Adaptive Filters Through Automatic Reconfiguration and Built-In Iterative Dividers ReAdapt-II：通过自动重新配置和内置迭代除法器优化 VLSI 自适应滤波器的能耗质量
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-09-04 DOI: 10.1109/tvlsi.2024.3446235
Pedro T. L. Pereira, Patrícia Ucker L. Costa, Eduardo da Costa, Paulo Flores, Sergio Bampi
{"title":"ReAdapt-II: Energy-Quality Optimizations for VLSI Adaptive Filters Through Automatic Reconfiguration and Built-In Iterative Dividers","authors":"Pedro T. L. Pereira, Patrícia Ucker L. Costa, Eduardo da Costa, Paulo Flores, Sergio Bampi","doi":"10.1109/tvlsi.2024.3446235","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3446235","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142194478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Second-Order Noise Shaping SAR ADC With Parallel Multiresidual Integrator 带并行多冗余积分器的二阶噪声整形 SAR ADC
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-30 DOI: 10.1109/tvlsi.2024.3447740
Yang Zhou, Wenjie Wang, Longbin Zhu, Zhengtao Zhu, Risheng Su, Jianan Zheng, Siyuan Xie, Jihong Li, Fanyi Meng, Zhijun Zhou, Keping Wang
{"title":"A Second-Order Noise Shaping SAR ADC With Parallel Multiresidual Integrator","authors":"Yang Zhou, Wenjie Wang, Longbin Zhu, Zhengtao Zhu, Risheng Su, Jianan Zheng, Siyuan Xie, Jihong Li, Fanyi Meng, Zhijun Zhou, Keping Wang","doi":"10.1109/tvlsi.2024.3447740","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3447740","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142194477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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