IEEE Transactions on Very Large Scale Integration (VLSI) Systems最新文献_第2页

TQ-SPUF: A Software PUF Design Based on HEVC Transform and Quantization Module for Device Security and Video Anti-Tampering TQ-SPUF：一种基于HEVC变换量化模块的设备安全和视频防篡改软件PUF设计

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-08-01 Epub Date: 2026-03-19 DOI: 10.1109/TVLSI.2026.3690749

Kejie Wang;Yuejun Zhang;Shuang Hu;Ziyu Zhou;Zhenkai Zhou;Huihong Zhang;Pengjun Wang

{"title":"TQ-SPUF: A Software PUF Design Based on HEVC Transform and Quantization Module for Device Security and Video Anti-Tampering","authors":"Kejie Wang;Yuejun Zhang;Shuang Hu;Ziyu Zhou;Zhenkai Zhou;Huihong Zhang;Pengjun Wang","doi":"10.1109/TVLSI.2026.3690749","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3690749","url":null,"abstract":"Addressing security threats faced by high efficiency video coding (HEVC) video devices in open deployment environments, this article proposes a HEVC Transform and Quantization (TQ)-based Software Physical Unclonable Function (TQ-SPUF). By overclocking the HEVC TQ module, this function induces clock violations on the critical path, thereby generating a stable and unique device fingerprint. Meanwhile, a two-stage postprocessing scheme combining majority voting and butterfly-<sc>xor operations is employed to generate stable and uniform device fingerprints. Based on the proposed TQ-SPUF, a lightweight challenge-response authentication protocol was designed to achieve device identity binding. Furthermore, the PUF-gated session key is utilized to drive a dual-perturbation selective encryption scheme, which introduces both fixed- and random-position perturbations into the I-frame network abstraction layer units. In this way, semantic information exploitable was effectively disrupted, thereby preventing content recovery or tampering. Experimental results show that the proposed TQ-SPUF achieves 98.84% randomness and 49.15% uniqueness, passing part of the NIST test. Moreover, the encrypted videos exhibit an average peak signal-to-noise ratio (PSNR) of 10.4313 dB and an average structural similarity index measure (SSIM) of 0.2935. This indicates that the encrypted content is visually incomprehensible, thereby achieving video anti-tampering protection.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 8","pages":"2545-2557"},"PeriodicalIF":3.2,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148627276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Memory-Optimized Constant Geometry NTT-Based Polynomial Multiplier With a Conflict-Free Bit-Reverse Reordering Method 基于无冲突逆位重排序方法的内存优化常几何ntt多项式乘法器

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-08-01 Epub Date: 2026-06-04 DOI: 10.1109/TVLSI.2026.3693877

Jinyang Hu;Yongkui Yang;Enyi Yao

{"title":"A Memory-Optimized Constant Geometry NTT-Based Polynomial Multiplier With a Conflict-Free Bit-Reverse Reordering Method","authors":"Jinyang Hu;Yongkui Yang;Enyi Yao","doi":"10.1109/TVLSI.2026.3693877","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3693877","url":null,"abstract":"The number theoretic transform (NTT) and its inverse (INTT) are frequently employed to accelerate polynomial multiplication, which represents both the core computational paradigm and the performance bottleneck in lattice-based cryptography (LBC). As an important variant in the NTT algorithm family, the constant geometry (CG) NTT has received significant attention from many researchers due to its simple and consistent memory access pattern. However, it suffers from two inherent and unsatisfactory limitations: its storage capacity requirement for <inline-formula> <tex-math>$boldsymbol {N}$ </tex-math></inline-formula> polynomial coefficients will exceed <inline-formula> <tex-math>$boldsymbol {N}$ </tex-math></inline-formula> to ensure conflict-free read and write; and it inevitably requires data relocation in memory between NTT and INTT. To address these challenges, this work proposes a modified ping-pong memory structure with reduced size and a novel conflict-free bit-reverse reordering method. For the modified ping-pong memory structure, each PE is allocated only two memory banks, and the overall storage requirement is reduced to <inline-formula> <tex-math>$1.5boldsymbol {N}$ </tex-math></inline-formula>. The proposed bit-reverse reordering algorithm, through simple logic and low-resource overhead, effectively avoids read–write conflicts and achieves seamless data relocation across the memory without stalling or additional space. Furthermore, we also introduce a lightweight twiddle factor memory access scheme, which, combined with the above techniques, drives down the resource consumption of both control logic and memory to a compact level. Finally, the FPGA implementation results of the proposed architecture demonstrate significant performance advantages over existing works in terms of area efficiency.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 8","pages":"2421-2433"},"PeriodicalIF":3.2,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148626426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Polar Code With Parity Check-Assisted Pruning for Error Correction in Modern Flash Memory 现代快闪记忆体中带奇偶校验辅助剪叶的极性码纠错

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-08-01 Epub Date: 2026-06-05 DOI: 10.1109/TVLSI.2026.3689019

Debao Wei;Huqi Xiang;Yongchao Wang;Zhelong Piao;Liyan Qiao

{"title":"Polar Code With Parity Check-Assisted Pruning for Error Correction in Modern Flash Memory","authors":"Debao Wei;Huqi Xiang;Yongchao Wang;Zhelong Piao;Liyan Qiao","doi":"10.1109/TVLSI.2026.3689019","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3689019","url":null,"abstract":"Three-dimensional (3-D) <sc>nand flash memory has emerged as the predominant solution for high-capacity nonvolatile data storage. However, the continuous increase in storage density has concurrently led to significant challenges in data reliability degradation. This article investigates the application of polar codes for error correction in <sc>nand Flash memory. We propose a combined Monte Carlo (CMC) method to dynamically determine information bit positions in polar code encoding for flash memory chips under varying reliability statuses. For decoding, we identify that the hard-decision read mechanism in flash memory introduces extreme log-likelihood ratio (LLR) quantization effects. This quantization phenomenon may erroneously prune correct decoding paths during successive cancellation list (SCL) decoding, thereby degrading the error correction capability of polar codes. To address this critical issue, we develop a cascaded parity-check (PC)-assisted path pruning scheme integrated with the SCL algorithm. The experimental results demonstrate that the proposed polar code algorithm can significantly enhance the reliability of data storage in <sc>nand flash memory. In the long code length scenario, the proposed polar decoding scheme with PC-assisted pruning achieves a maximum uncorrectable bit error rate (UBER) reduction of 98.62% compared to algorithms without PC. The proposed approach demonstrates an 8.56 times increase in the raw bit error rate (RBER) threshold for achieving 100% error correction success, significantly surpassing the performance of conventional low-density parity-check (LDPC) codes, especially toward the end of the flash memory’s lifespan.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 8","pages":"2582-2594"},"PeriodicalIF":3.2,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148628347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Self-Feeding-Priority SECE for Piezoelectric Energy Harvesting From Diverse Kinetic Energy 基于自馈优先的压电能量收集系统

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-08-01 Epub Date: 2026-03-06 DOI: 10.1109/TVLSI.2026.3687854

Xiudeng Wang;Yijun Wei;Libo Qian;Zhangming Zhu

引用次数: 0

A 7.33 nW Ratio Wake-Up Timer With XO and Auxiliary Oscillator for Real-Time Shock Recovery 具有XO和辅助振荡器的7.33 nW比唤醒定时器，用于实时冲击恢复

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-08-01 Epub Date: 2026-06-02 DOI: 10.1109/TVLSI.2026.3695454

Ehab A. Hamed;Inhee Lee

{"title":"A 7.33 nW Ratio Wake-Up Timer With XO and Auxiliary Oscillator for Real-Time Shock Recovery","authors":"Ehab A. Hamed;Inhee Lee","doi":"10.1109/TVLSI.2026.3695454","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3695454","url":null,"abstract":"Precision timing is a fundamental requirement for ultralow-power Internet-of-Things (IoT) nodes, wildlife trackers, and wearable health devices. However, maintaining accuracy in these severely power-constrained systems is difficult due to the mechanical shock sensitivity of crystal oscillators (XOs). This work proposes a ratio wake-up timer (Ratio-WUT) designed to enhance XO shock resilience with very low power overhead. The system integrates a 5.58 nW XO with a secondary ultralow-power auxiliary oscillator (AuxO). A 1.75 nW digital controller actively monitors the ratio between XO and AuxO cycles, triggering an autonomous restart sequence immediately upon detecting an XO failure. Unlike conventional hybrid timers that rely on periodic wake-up checks, the Ratio-WUT provides continuous, real-time fault detection and correction. The prototype features a custom 180 nm CMOS XO and subthreshold AuxO, with control logic validated on an FPGA. Detailed postlayout analysis of a fully integrated version estimates a total power consumption of 7.33 nW. Experimental validation confirms the system’s ability to recover from mechanical shock events in real-time while maintaining wake-up functionality. By leveraging the inherent stability of the XO for timing while using the AuxO for supervision, the Ratio-WUT achieves a <inline-formula> <tex-math>$3.85times $ </tex-math></inline-formula> power reduction compared to prior hybrid architectures.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 8","pages":"2681-2685"},"PeriodicalIF":3.2,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148626257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Identifying Failing Flip-Flops in Scan-Based Designs Using Highly Compressed Test Results 使用高度压缩的测试结果识别基于扫描的设计中的故障触发器

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-08-01 Epub Date: 2026-03-14 DOI: 10.1109/TVLSI.2026.3691865

Grzegorz Mrugalski;Janusz Rajski;Maciej Trawka;Jerzy Tyszer

{"title":"Identifying Failing Flip-Flops in Scan-Based Designs Using Highly Compressed Test Results","authors":"Grzegorz Mrugalski;Janusz Rajski;Maciej Trawka;Jerzy Tyszer","doi":"10.1109/TVLSI.2026.3691865","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3691865","url":null,"abstract":"The semiconductor industry makes a major change by moving from FinFETs to lower technology nodes with angstrom-scale nanowire or nanosheet gate-all-around transistors. Keeping to Moore’s law, this pace of miniaturization coupled with heterogeneous integration of multiple dies into single packages has led to exponentially complex, tightly structured, and massively interconnected chiplets comprising trillions of transistors. These designs are inherently bound to witness new failure phenomena, including those causing elusive silent data errors. Typically, one of the first steps in an attempt to locate actual defects within a chiplet using scan chains and test compression is to identify failing flip-flops, i.e., memory elements (also known as scan cells) receiving erroneous signals. This article presents a novel scheme to address this challenge based on highly compressed production test outcomes. The scheme uses a simple, yet effective, test response compactor producing three companion signatures in space and time domains. The advantage of the scheme, further referred to as a triangular compaction, is its generic hardware, which, in conjunction with a highly parallel offline software, is capable of accurately identifying large failing flip-flop sets by narrowing the search space down to just a few equivalent solutions. No additional heuristics are needed to guide this process. The proposed scheme is well positioned to play a crucial role in rapid first silicon bring-up and debug or high-volume production fault diagnosis. This has been confirmed on production data from several industrial cores and is reported herein.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 8","pages":"2595-2606"},"PeriodicalIF":3.2,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148626091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Multibit ΔΣ TDC With Space--Time Averaging for UWB Transceivers Achieving ToF-Based Fine Ranging 用于实现基于tof的精细测距的UWB收发器的多位ΔΣ时空平均TDC

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-08-01 Epub Date: 2026-03-19 DOI: 10.1109/TVLSI.2026.3692273

Minsong Zhang;Bowen Wang;Nannan Shi;Xin An;Rong Zhou;Zhangming Zhu

{"title":"A Multibit ΔΣ TDC With Space--Time Averaging for UWB Transceivers Achieving ToF-Based Fine Ranging","authors":"Minsong Zhang;Bowen Wang;Nannan Shi;Xin An;Rong Zhou;Zhangming Zhu","doi":"10.1109/TVLSI.2026.3692273","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3692273","url":null,"abstract":"This work presents a multibit <inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula> time-to-digital converter (TDC) employing a space–time averaging (STA) technique, designed for ultrawideband (UWB) transceivers to achieve fine-resolution time-of-flight (ToF) ranging. The proposed TDC offers both high time resolution and strong immunity to bit errors. By dynamically controlling the input reference signals of multiple phase detectors (PDs), the STA technique significantly reduces the quantization error of the <inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula> TDC, thereby achieving fine time resolution with a limited oversampling ratio (OSR). Additionally, by introducing a delay in the PD reset path, the TDC provides strong immunity to bit errors caused by UWB receiver misdetection. Implemented in 65-nm CMOS, the proposed multibit <inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula> TDC achieves a root-mean-square (rms) error of 14.43 ps with an OSR of 50, consuming <inline-formula> <tex-math>$276.5~mu $ </tex-math></inline-formula>W at a 10-MHz clock frequency from a 1-V supply.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 8","pages":"2646-2650"},"PeriodicalIF":3.2,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148626602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Hardware-Efficient Reed--Solomon Decoding Architecture for Single-Symbol Error Correcting in High-Bandwidth Memory 高带宽存储器中单符号纠错的硬件高效Reed- Solomon解码结构

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-08-01 Epub Date: 2026-03-15 DOI: 10.1109/TVLSI.2026.3692208

Jaehoon Kwon;Jeongmin Kim;Jeonghyeon Yoon;Hansol Jeong;In-Cheol Park

{"title":"A Hardware-Efficient Reed--Solomon Decoding Architecture for Single-Symbol Error Correcting in High-Bandwidth Memory","authors":"Jaehoon Kwon;Jeongmin Kim;Jeonghyeon Yoon;Hansol Jeong;In-Cheol Park","doi":"10.1109/TVLSI.2026.3692208","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3692208","url":null,"abstract":"The JEDEC HBM3 standard mandates a (19, 17) single-symbol-error-correcting (SSEC) Reed–Solomon (RS) code with 16-bit symbols, requiring hardware implementations to satisfy stringent area and latency constraints. While SSEC decoding is simpler than general multisymbol correction, conventional architectures still rely on Galois field (GF) inverse operations, leading to substantial look-up table (LUT) overhead. This brief proposes an area-efficient, high-speed SSEC RS decoding architecture specifically optimized for the high-bandwidth memory (HBM) environment. By exploiting the short message length of the (19, 17) code, the proposed design restricts decoding operations to a limited set of GF elements, effectively eliminating the need for expensive GF inverse LUTs. Instead, error location and magnitude are determined through a comparison-based search and constant GF multiplications. Synthesis results in 28-nm CMOS technology demonstrate that the proposed architecture achieves up to 97% area reduction compared to conventional decoder implementations. Furthermore, it improves operating speed by up to 81% over algorithmic baselines. These results confirm the superior efficiency and scalability of the proposed design for highly integrated, latency-critical memory systems such as HBM3.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 8","pages":"2666-2670"},"PeriodicalIF":3.2,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148626612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low-Complexity Parallel Syndrome Computation and Chien Search Architecture Based on Reed--Muller Transform 基于Reed- Muller变换的低复杂度并行综合征计算与简搜索结构

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-08-01 Epub Date: 2026-03-11 DOI: 10.1109/TVLSI.2026.3689292

Muxun Zhang;Suwen Song;Liyang Zhou

{"title":"Low-Complexity Parallel Syndrome Computation and Chien Search Architecture Based on Reed--Muller Transform","authors":"Muxun Zhang;Suwen Song;Liyang Zhou","doi":"10.1109/TVLSI.2026.3689292","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3689292","url":null,"abstract":"Bose–Chaudhuri–Hocquenghem (BCH) and Reed–Solomon (RS) codes have been widely adopted in communication systems (such as Ethernet) and storage applications. The ever-increasing data transmission rates impose higher throughput demands on RS/BCH decoders, necessitating a higher degree of parallelism in their key computing modules–syndrome computation (SC) and Chien search (CS), which significantly increases the hardware complexity. The Reed–Muller (RM) transform has been introduced to reduce complexity, which decomposes a special class of Vandermonde matrices into a sparse matrix and an RM matrix. However, its fully parallel requirement renders it infeasible in real-world systems. In this article, we propose a novel partially parallel algorithm based on RM transform for SC and CS modules. First, the computation matrix required by the RM transform is partitioned according to power-of-two parallelism, and a set of transform matrices is constructed to enable mutual conversion, thereby allowing partial parallelization of both the SC and CS modules. Then, the original RM transform is applied to the partitioned matrices to preserve the inherent low-complexity advantage. Finally, we elaborately design the corresponding hardware architecture, in which a flexible matrix-reuse strategy is proposed to further reduce hardware cost. Synthesized under 28-nm CMOS technology, the proposed SC architecture achieves up to 45% area reduction compared with state-of-the-art algorithms.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 8","pages":"2397-2407"},"PeriodicalIF":3.2,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148627848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

MoS2-Enhanced Antisymmetric 2T2R Logic Unit for One-Step Write/Compute In-Memory XNOR in BNN Accelerators 用于BNN加速器中单步写入/计算内存XNOR的mos2增强反对称2T2R逻辑单元

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-08-01 Epub Date: 2026-03-15 DOI: 10.1109/TVLSI.2026.3691526

Zhoujie Pan;Yuwan Hong;Dingyi Zhang;Yanming Liu;He Tian

{"title":"MoS2-Enhanced Antisymmetric 2T2R Logic Unit for One-Step Write/Compute In-Memory XNOR in BNN Accelerators","authors":"Zhoujie Pan;Yuwan Hong;Dingyi Zhang;Yanming Liu;He Tian","doi":"10.1109/TVLSI.2026.3691526","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3691526","url":null,"abstract":"The rise of artificial intelligence (AI) and growing energy constraints have intensified the need for efficient, low-power hardware. The <sc>xnor logic, a cornerstone of low-precision neural network inference, is especially critical to optimize for energy efficiency. Conventional CMOS-based in-memory <sc>xnor units, however, face key limitations, including low integration density, readout interference, and multistep write protocols. To address these challenges, we present a MoS2 transistor-enhanced antisymmetric 2T2R in-memory <sc>xnor logic unit, enabling both write and compute operations to be finished within a single step, achieving the theoretical minimum for in-memory logic primitives. Beyond logic-level optimization, the incorporation of MoS2 transistors facilitates monolithic 3-D integration and lowers static power consumption relative to standard CMOS devices. At the system level, we extend the analog majority architecture to BNN inference, including the weight mapping strategy, and discuss the system-level advantages and quantization errors introduced by this approach.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 8","pages":"2656-2660"},"PeriodicalIF":3.2,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148628064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0