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IEEE Transactions on Very Large Scale Integration (VLSI) Systems最新文献

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A 0.05–1.5-GHz PVT-Insensitive Digital-to-Time Converter for QKD Applications 用于 QKD 应用的 0.05-1.5 GHz PVT 不敏感数时转换器
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-30 DOI: 10.1109/tvlsi.2024.3447111
Haiyue Yan, Yan Ye, Wenjia Li, Xuefei Bai
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引用次数: 0
Power-Efficient Analog Hardware Architecture of the Learning Vector Quantization Algorithm for Brain Tumor Classification 用于脑肿瘤分类的学习矢量量化算法的高能效模拟硬件架构
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-30 DOI: 10.1109/tvlsi.2024.3447903
Vassilis Alimisis, Emmanouil Anastasios Serlis, Andreas Papathanasiou, Nikolaos P. Eleftheriou, Paul P. Sotiriadis
{"title":"Power-Efficient Analog Hardware Architecture of the Learning Vector Quantization Algorithm for Brain Tumor Classification","authors":"Vassilis Alimisis, Emmanouil Anastasios Serlis, Andreas Papathanasiou, Nikolaos P. Eleftheriou, Paul P. Sotiriadis","doi":"10.1109/tvlsi.2024.3447903","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3447903","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142194475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
HPR-Mul: An Area and Energy-Efficient High-Precision Redundancy Multiplier by Approximate Computing HPR-Mul：通过近似计算实现面积和能效的高精度冗余乘法器
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-29 DOI: 10.1109/tvlsi.2024.3445108
Jafar Vafaei, Omid Akbari
{"title":"HPR-Mul: An Area and Energy-Efficient High-Precision Redundancy Multiplier by Approximate Computing","authors":"Jafar Vafaei, Omid Akbari","doi":"10.1109/tvlsi.2024.3445108","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3445108","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142194479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A CMOS Readout Circuit for Resistive Tactile Sensor Array Using Crosstalk Suppression and Nonuniformity Compensation Techniques 采用串音抑制和不均匀性补偿技术的电阻式触觉传感器阵列 CMOS 读出电路
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-27 DOI: 10.1109/tvlsi.2024.3447164
Yao Li, Junfeng Geng, Mao Ye, Jiaji He, Xiaoxiao Zheng, Qiuwei Wang, Yiqiang Zhao
{"title":"A CMOS Readout Circuit for Resistive Tactile Sensor Array Using Crosstalk Suppression and Nonuniformity Compensation Techniques","authors":"Yao Li, Junfeng Geng, Mao Ye, Jiaji He, Xiaoxiao Zheng, Qiuwei Wang, Yiqiang Zhao","doi":"10.1109/tvlsi.2024.3447164","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3447164","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142194481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Spread Spectrum-Based Countermeasures for Cryptographic RISC-V SoC 基于扩频的密码 RISC-V SoC 对策
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-27 DOI: 10.1109/tvlsi.2024.3444851
Thai-Ha Tran, Ba-Anh Dao, Duc-Hung Le, Van-Phuc Hoang, Trong-Thuc Hoang, Cong-Kha Pham
{"title":"Spread Spectrum-Based Countermeasures for Cryptographic RISC-V SoC","authors":"Thai-Ha Tran, Ba-Anh Dao, Duc-Hung Le, Van-Phuc Hoang, Trong-Thuc Hoang, Cong-Kha Pham","doi":"10.1109/tvlsi.2024.3444851","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3444851","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142194480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Detect and Replace: Efficient Soft Error Protection of FPGA-Based CNN Accelerators 检测和替换：基于 FPGA 的 CNN 加速器的高效软错误保护
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-26 DOI: 10.1109/tvlsi.2024.3443834
Zhen Gao, Yanmao Qi, Jinchang Shi, Qiang Liu, Guangjun Ge, Yu Wang, Pedro Reviriego
{"title":"Detect and Replace: Efficient Soft Error Protection of FPGA-Based CNN Accelerators","authors":"Zhen Gao, Yanmao Qi, Jinchang Shi, Qiang Liu, Guangjun Ge, Yu Wang, Pedro Reviriego","doi":"10.1109/tvlsi.2024.3443834","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3443834","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142194488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information IEEE 超大规模集成 (VLSI) 系统论文集 出版信息
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-26 DOI: 10.1109/TVLSI.2024.3422690
{"title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information","authors":"","doi":"10.1109/TVLSI.2024.3422690","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3422690","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10648914","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142077671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information 电气和电子工程师学会超大规模集成 (VLSI) 系统学会论文集信息
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-26 DOI: 10.1109/TVLSI.2024.3435251
{"title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information","authors":"","doi":"10.1109/TVLSI.2024.3435251","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3435251","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10648917","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142077622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Single-Stage Gain-Boosted Cascode Amplifier With Three-Layer Cascode Feedback Amplifier for Front-End SHA in High-Linearity Pipelined ADC 用于高线性度流水线 ADC 前端 SHA 的带有三层级联反馈放大器的单级增益级联放大器
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-19 DOI: 10.1109/tvlsi.2024.3439374
Yu Liu, Yupeng Shen, Mingliang Chen, Hui Xu, Xubin Chen, Jiarui Liu, Zhiyu Wang, Faxin Yu
{"title":"A Single-Stage Gain-Boosted Cascode Amplifier With Three-Layer Cascode Feedback Amplifier for Front-End SHA in High-Linearity Pipelined ADC","authors":"Yu Liu, Yupeng Shen, Mingliang Chen, Hui Xu, Xubin Chen, Jiarui Liu, Zhiyu Wang, Faxin Yu","doi":"10.1109/tvlsi.2024.3439374","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3439374","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142194483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 65 nm CMOS Analog Programmable Standard Cell Library for Mixed-Signal Computing 用于混合信号计算的 65 纳米 CMOS 模拟可编程标准单元库
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-19 DOI: 10.1109/tvlsi.2024.3432916
Pranav O. Mathews, Praveen Raj Ayyappan, Afolabi Ige, Swagat Bhattacharyya, Linhao Yang, Jennifer O. Hasler
{"title":"A 65 nm CMOS Analog Programmable Standard Cell Library for Mixed-Signal Computing","authors":"Pranav O. Mathews, Praveen Raj Ayyappan, Afolabi Ige, Swagat Bhattacharyya, Linhao Yang, Jennifer O. Hasler","doi":"10.1109/tvlsi.2024.3432916","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3432916","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142194482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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