IEEE Transactions on Very Large Scale Integration (VLSI) Systems最新文献_第2页

Analysis of a Delay-Element-Based Technique for Enhancing Soft Error Tolerance at Input Nodes Around Clock Edges 基于延迟单元的时钟边输入节点软容错技术分析

IF 3.1 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-12-22 DOI: 10.1109/TVLSI.2025.3643939

Song Wang;Kazuteru Namba

引用次数: 0

An Energy-Efficient Edge Coprocessor for Neural Rendering With Explicit Data Reuse Strategies 基于显式数据重用策略的神经渲染节能边缘协处理器

IF 3.1 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-12-17 DOI: 10.1109/TVLSI.2025.3641653

Binzhe Yuan;Xiangyu Zhang;Zeyu Zheng;Yuefeng Zhang;Haochuan Wan;Zhechen Yuan;Junsheng Chen;Yunxiang He;Junran Ding;Xiaoming Zhang;Chaolin Rao;Wenyan Su;Pingqiang Zhou;Jingyi Yu;Xin Lou

{"title":"An Energy-Efficient Edge Coprocessor for Neural Rendering With Explicit Data Reuse Strategies","authors":"Binzhe Yuan;Xiangyu Zhang;Zeyu Zheng;Yuefeng Zhang;Haochuan Wan;Zhechen Yuan;Junsheng Chen;Yunxiang He;Junran Ding;Xiaoming Zhang;Chaolin Rao;Wenyan Su;Pingqiang Zhou;Jingyi Yu;Xin Lou","doi":"10.1109/TVLSI.2025.3641653","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3641653","url":null,"abstract":"Neural radiance fields (NeRFs) have transformed 3-D reconstruction and rendering, facilitating photorealistic image synthesis from sparse viewpoints. This work introduces an explicit data reuse neural rendering (EDR-NR) architecture, which reduces frequent external memory accesses (EMAs) and cache misses by exploiting the spatial locality from three phases, including rays, ray packets (RPs), and samples. The EDR-NR architecture features a four-stage scheduler that clusters rays on the basis of <inline-formula> <tex-math>$Z$ </tex-math></inline-formula>-order, prioritize lagging rays when ray divergence happens, reorders RPs based on spatial proximity, and issues samples out-of-orderly (OoO) according to the availability of on-chip feature data. In addition, a four-tier hierarchical RP marching (HRM) technique is integrated with an axis-aligned bounding box (AABB) to facilitate spatial skipping (SS), reducing redundant computations and improving throughput. Moreover, a balanced allocation strategy for feature storage is proposed to mitigate SRAM bank conflicts. Fabricated using a 40-nm process with a die area of 10.5 mm<sup>2</sup>, the EDR-NR chip demonstrates a <inline-formula> <tex-math>$2.41times $ </tex-math></inline-formula> enhancement in normalized energy efficiency, a <inline-formula> <tex-math>$1.21times $ </tex-math></inline-formula> improvement in normalized area efficiency, a <inline-formula> <tex-math>$1.20times $ </tex-math></inline-formula> increase in normalized throughput, and a 53.42% reduction in on-chip SRAM consumption compared with state-of-the-art accelerators.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 2","pages":"620-633"},"PeriodicalIF":3.1,"publicationDate":"2025-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146015922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Area-Efficient and Low-Latency ASIC Design of Deflate Data Compressor for SSD Applications 一种面向SSD应用的放气数据压缩器的面积高效低延迟ASIC设计

IF 3.1 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-12-17 DOI: 10.1109/TVLSI.2025.3642311

Nengyuan Sun;Ming Jin;Jianghong Li;Zhaoyi Niu;Jinghe Wang;Zhiyuan Pan;Jiafeng Cheng;Wenrui Liu;Kai Shi;Jiaqi Wang;Jiawei Zhang;Linhan Wang;Kangning Song;Xinyu Chen;Haoxiang Yu;Weize Yu

{"title":"An Area-Efficient and Low-Latency ASIC Design of Deflate Data Compressor for SSD Applications","authors":"Nengyuan Sun;Ming Jin;Jianghong Li;Zhaoyi Niu;Jinghe Wang;Zhiyuan Pan;Jiafeng Cheng;Wenrui Liu;Kai Shi;Jiaqi Wang;Jiawei Zhang;Linhan Wang;Kangning Song;Xinyu Chen;Haoxiang Yu;Weize Yu","doi":"10.1109/TVLSI.2025.3642311","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3642311","url":null,"abstract":"In this brief, a high-speed [multiway parallel (MWP)] hardware-implemented deflate data compressor (DDC) is proposed for reducing the storage of solid-state drives (SSDs). To minimize the area of the DDC, registers instead of static random access memories (SRAMs) are utilized for building hash tables because multiway data within the DDC are able to access a register-based hash table simultaneously. To further reduce the area of the DDC, the output data of indefinite length are concatenated with a tree-type hardware architecture for reducing the overall concatenation complexity. Moreover, a solid mathematical foundation is established for optimizing the latency values of Lempel–Ziv (LZ)77 circuit, the Huffman encoding circuit, and the output data concatenation circuit within the MWP DDC. The results show that the proposed MWP DDC is capable of achieving a 12.1-Gb/s throughput and a 1.76 compression ratio (CR) with a 1.17-mm<sup>2</sup> area and 0.103-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>s latency, under the synthesis of SMIC 55-nm process design kits (PDKs). Hence, the proposed DDC satisfies the SSD compression requirement for a universal serial bus (USB) 3.2 connector.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 3","pages":"1057-1061"},"PeriodicalIF":3.1,"publicationDate":"2025-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147280527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Area-Efficient Noise-Shaping SAR ADC With Parallel-Delayed Sampling 一种具有并行延迟采样的面积高效噪声整形SAR ADC

IF 3.1 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-12-15 DOI: 10.1109/TVLSI.2025.3642291

Zhengtao Zhu;Wenjie Wang;Fan Luo;Longbin Zhu;Zhijun Zhou;Keping Wang

{"title":"An Area-Efficient Noise-Shaping SAR ADC With Parallel-Delayed Sampling","authors":"Zhengtao Zhu;Wenjie Wang;Fan Luo;Longbin Zhu;Zhijun Zhou;Keping Wang","doi":"10.1109/TVLSI.2025.3642291","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3642291","url":null,"abstract":"This brief presents an area-efficient noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) employing a parallel-delayed sampling (PDS) technique. PDS samples the residual voltages from multiple ADC conversion cycles to increase the NS effect, without the need for large integration capacitors of the typical cascaded passive integrators. A preamplifier is placed between the sampling capacitors and the integrator to avoid signal attenuation, while further reducing the area of the integrator. PDS and preamplifier introduce two left-half-plane poles to the noise transfer function (NTF) to boost the NS effect, while reducing the impact of the parasitic capacitance to essentially enhance the robustness. A prototype 9-bit NS-SAR ADC is designed in a 130-nm CMOS process. At an oversampling ratio (OSR) of 16, the proposed PDS NS-SAR ADC achieves 80.93-dB peak signal to noise and distortion ratio (SNDR) and provides 4.2 NS/area efficiency factor. It consumes a power of <inline-formula> <tex-math>$23.46~mu $ </tex-math></inline-formula>W over a bandwidth of 19.53 kHz, achieving a Schreier figure of merit (FoM<inline-formula> <tex-math>${}_{mathrm {S}}$ </tex-math></inline-formula>) of 170.13 dB.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 3","pages":"1053-1056"},"PeriodicalIF":3.1,"publicationDate":"2025-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147280904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

FADE: Fault-Aware Adaptive On-Die ECC for Improving Robustness 衰减：用于提高鲁棒性的故障感知自适应芯片内ECC

IF 3.1 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-12-10 DOI: 10.1109/TVLSI.2025.3640215

Youngki Moon;Juyong Lee;Nayeun Kim;Yeonho Choi;Byungsoo Kim;Sungho Kang

{"title":"FADE: Fault-Aware Adaptive On-Die ECC for Improving Robustness","authors":"Youngki Moon;Juyong Lee;Nayeun Kim;Yeonho Choi;Byungsoo Kim;Sungho Kang","doi":"10.1109/TVLSI.2025.3640215","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3640215","url":null,"abstract":"The increasing density of dynamic random access memory (DRAM) renders permanent faults and soft errors more prevalent, which critically reduces yield and reliability. Although error correction code (ECC) can mitigate this issue, existing ECCs are not optimized for fault correction. As a result, fault tolerance remains insufficient, and the error correction capability in the presence of faults is degraded. Therefore, to improve DRAM robustness by efficiently addressing both permanent faults and soft errors, this brief proposes a fault-aware adaptive on-die ECC (FADE) in which two ECC engines independently operate in either fault mode (FM) or error mode (EM) according to the number of faulty symbols (FSs). In FM, a fault polynomial is reconstructed by reusing the fault addresses that the built-in self-repair (BISR) stores in content-addressable memory (CAM). To calculate the corresponding fault magnitudes, a modified decoding equation is employed. As a result, the number of correctable FSs in FM doubles compared to the conventional ECC. Moreover, with the proposed symbol-based fault isolation, both fault tolerance and error correction capability in the presence of faults are drastically enhanced. Additionally, the experimental results show that the proposed design can be implemented with a reasonable overhead in terms of delay and area.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 2","pages":"707-710"},"PeriodicalIF":3.1,"publicationDate":"2025-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146015951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Analytical Model of Mismatch Dominance Crossover in High-Speed Flash ADC Cores 高速闪存ADC核中失配优势交叉的分析模型

IF 3.1 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-12-09 DOI: 10.1109/TVLSI.2025.3637272

Shatadal Chatterjee;Jitumani Sarma

{"title":"An Analytical Model of Mismatch Dominance Crossover in High-Speed Flash ADC Cores","authors":"Shatadal Chatterjee;Jitumani Sarma","doi":"10.1109/TVLSI.2025.3637272","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3637272","url":null,"abstract":"The flash analog-to-digital converters (ADCs), essential for high-speed embedded systems, face inherent linearity constraints due to device mismatch in the resistor ladder and comparator stages. While individual analytical models exist for these mismatch sources, designers rely on Monte Carlo simulations to evaluate the combined errors. This brief introduces a unified analytical framework with closed-form expressions that capture both mismatch sources, enabling efficient estimation of root mean square (rms) integral nonlinearity/differential nonlinearity (INL/DNL). Validated against circuit simulations, the model achieves a mean absolute error (MAE) of 2.71% (<inline-formula> <tex-math>$boldsymbol {sigma _{textbf {DNL}}}$ </tex-math></inline-formula>) and 2.51% (<inline-formula> <tex-math>$sigma _{text {INL}}$ </tex-math></inline-formula>), and the maximum absolute error (MaxE) remains within 5.44%. This predictive capability guides high-yield, precision, power, and area (PPA)-optimized system-on-chip (SoC) design, enabling over <inline-formula> <tex-math>$3{times }$ </tex-math></inline-formula> silicon area reduction through application-specific optimization.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 2","pages":"702-706"},"PeriodicalIF":3.1,"publicationDate":"2025-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146015933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Pattern-Dependent Pulse Filtering Technique for Low-Jitter Injection-Locked CDR in 28-nm CMOS 用于低抖动注入锁定CDR的模式相关脉冲滤波技术

IF 3.1 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-12-09 DOI: 10.1109/TVLSI.2025.3639588

Junhak Kim;Young-Wook Kim;Sinho Lee;Yoojin Jung;Min-Seong Choo;Kwanseo Park

引用次数: 0

A 0.38-mW, 50-MS/s, 2.3-μApp Current-Integration SAR-Based Current-to-Digital Converter for Real-Time OCT Imaging 用于实时OCT成像的0.38 mw, 50 ms /s， 2.3 μ app电流集成sar电流-数字转换器

IF 3.1 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-12-02 DOI: 10.1109/TVLSI.2025.3634734

Xiao Wang;Xin Sun;Yibin Zheng;Runkun Li;Kong-Pang Pun

引用次数: 0

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information 超大规模集成电路（VLSI）系统学报

IF 3.1 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-11-25 DOI: 10.1109/TVLSI.2025.3630312

引用次数: 0

Corrections to “Efficient Fault-Detection Architectures for Barrett Reduction and Multiplication in Classical and Post-Quantum Cryptographic Systems” 对“经典和后量子密码系统中用于巴雷特约简和乘法的有效故障检测架构”的修正

IF 3.1 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-11-25 DOI: 10.1109/TVLSI.2025.3621790

Saeed Aghapour;Kiarash Sedghighadikolaei;Attila A. Yavuz;Bechir Hamdaoui;Mehran Mozaffari-Kermani

引用次数: 0