IEEE Transactions on Very Large Scale Integration (VLSI) Systems最新文献_第2页

An Area and Energy-Efficient Systolic Array Accelerator Architecture for Deep Neural Networks Using Stochastic Computing 基于随机计算的深度神经网络收缩阵列加速器结构

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-03-24 DOI: 10.1109/TVLSI.2025.3550786

Jingwei Zhu;Jingguo Wu;Zongru Yang;Yu Jiang;Yun Chen

{"title":"An Area and Energy-Efficient Systolic Array Accelerator Architecture for Deep Neural Networks Using Stochastic Computing","authors":"Jingwei Zhu;Jingguo Wu;Zongru Yang;Yu Jiang;Yun Chen","doi":"10.1109/TVLSI.2025.3550786","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3550786","url":null,"abstract":"Deep neural networks (DNNs) are widely used to handle various intelligent tasks. With the increased model size, the DNNs’ hardware accelerators are challenging the higher area overhead and energy consumption. Stochastic computing (SC) has recently been considered for implementing DNNs and reducing hardware consumption. However, many current SC-based DNN accelerators fail to balance accuracy, performance, and resource overhead. In addition, their limited scalability and flexibility restrict their use in edge devices. In this article, we design an area and energy-efficient DNN accelerator architecture using SC. We propose an SC-binary hybrid processing unit with piecewise shift compensation without significant additional hardware overhead increment to improve the SC accuracy. To balance performance and resource overhead, we conduct a design space exploration (DSE) from an overall architectural perspective. An experimental platform with both software and hardware for SC-based DNNs is established. The software simulation results demonstrate that the best accuracy of the designed SC-DNN on the CIFAR-10 is 91.9%, which is 3.2% higher than that of the previous SC-DNN work. The VLSI implementation of the hardware is synthesized using the TSMC 28-nm CMOS process. Results show that compared to the binary computing counterpart, our design achieves <inline-formula> <tex-math>$2.7times $ </tex-math></inline-formula> area efficiency and <inline-formula> <tex-math>$3.4times $ </tex-math></inline-formula> energy efficiency. Compared to other SC-DNN accelerator designs, our design can provide <inline-formula> <tex-math>$5.3times $ </tex-math></inline-formula> area efficiency and <inline-formula> <tex-math>$7.3times $ </tex-math></inline-formula> energy efficiency.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 6","pages":"1582-1595"},"PeriodicalIF":2.8,"publicationDate":"2025-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144117276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information IEEE超大规模集成电路（VLSI）系统学报

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-03-22 DOI: 10.1109/TVLSI.2025.3568415

引用次数: 0

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information 超大规模集成电路（VLSI）系统学报

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-03-22 DOI: 10.1109/TVLSI.2025.3568413

引用次数: 0

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information IEEE超大规模集成电路（VLSI）系统学报

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-03-21 DOI: 10.1109/TVLSI.2025.3549990

引用次数: 0

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information 超大规模集成电路（VLSI）系统学报

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-03-21 DOI: 10.1109/TVLSI.2025.3549993

引用次数: 0

ResiLogic: Leveraging Composability and Diversity to Design Fault and Intrusion Resilient Chips 弹性逻辑：利用可组合性和多样性来设计故障和入侵弹性芯片

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-03-20 DOI: 10.1109/TVLSI.2025.3544860

Ahmad T. Sheikh;Ali Shoker;Suhaib A. Fahmy;Paulo Esteves-Verissimo

{"title":"ResiLogic: Leveraging Composability and Diversity to Design Fault and Intrusion Resilient Chips","authors":"Ahmad T. Sheikh;Ali Shoker;Suhaib A. Fahmy;Paulo Esteves-Verissimo","doi":"10.1109/TVLSI.2025.3544860","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3544860","url":null,"abstract":"A long-standing challenge is the design of chips resilient to faults and glitches. Both fine-grained gate diversity and coarse-grained modular redundancy have been used in the past. However, these approaches have not been well-studied under other threat models where some stakeholders in the supply chain are untrusted. Increasing digital sovereignty tensions raise concerns regarding the use of foreign off-the-shelf tools and intellectual property (IP), or off-sourcing fabrication, driving research into the design of resilient chips under this threat model. This article addresses a threat model considering three pertinent attacks to resilience: distribution, zonal, and compound attacks. To mitigate these attacks, we introduce the <italic>ResiLogic</i> framework that exploits <italic>Diversity by Composability</i>: constructing diverse circuits composed of smaller diverse ones by design. This approach enables designers to develop circuits in the early stages of design without the need for additional redundancy in terms of space or cost. To generate diverse circuits, we propose a technique using E-Graphs with new rewrite definitions for diversity. Using this approach at different levels of granularity is shown to improve the resilience of circuit design in <italic>ResiLogic</i> up to <inline-formula> <tex-math>$times 5$ </tex-math></inline-formula> against the three considered attacks.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 6","pages":"1751-1764"},"PeriodicalIF":2.8,"publicationDate":"2025-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144117383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Metastable-Dither-Based Digital Background Calibration of Interstage Gain Nonlinearity in Pipelined SAR ADC 基于亚稳抖动的流水式SAR ADC级间增益非线性数字背景校正

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-03-17 DOI: 10.1109/TVLSI.2025.3544825

Le Chen;Yue Cao;Lin Ling;Shubin Liu;Haolin Han

引用次数: 0

Information Leakage Through Physical Layer Supply Voltage Coupling Vulnerability 通过物理层电源电压耦合漏洞泄露信息

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-03-17 DOI: 10.1109/TVLSI.2025.3545804

Sahan Sanjaya;Aruna Jayasena;Prabhat Mishra

{"title":"Information Leakage Through Physical Layer Supply Voltage Coupling Vulnerability","authors":"Sahan Sanjaya;Aruna Jayasena;Prabhat Mishra","doi":"10.1109/TVLSI.2025.3545804","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3545804","url":null,"abstract":"Power side-channel attacks are widely known for extracting information from data processed within a device while assuming that an attacker has physical access or the ability to modify the device. In this article, we introduce a novel side-channel vulnerability that leaks data-dependent power variations through physical layer supply voltage coupling (PSVC). Unlike traditional power side-channel attacks, the proposed vulnerability allows an adversary to mount an attack and extract information without modifying the device. In addition, unlike existing power-based remote attacks on field-programmable gate arrays (FPGAs), the PSVC vulnerability applies to both on-chip and on-board attacks. We assess the effectiveness of the PSVC vulnerability through three case studies, demonstrating several end-to-end attacks on general-purpose microcontrollers with varying adversary capabilities. These case studies provide evidence for the existence of the PSVC vulnerability, its applicability to on-chip as well as on-board side-channel attacks, and how it can eliminate the need for physical access to the target device, making it applicable to any off-the-shelf hardware. Our experiments also reveal that designing devices to operate at the lowest operational voltage significantly reduces the risk of PSVC side-channel vulnerability.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 6","pages":"1715-1728"},"PeriodicalIF":2.8,"publicationDate":"2025-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144117270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 12-bit 2-GS/s Pipeline ADC in 28-nm CMOS With Linear-Error Self-Calibration 具有线性误差自校准的28纳米CMOS 12位2-GS/s流水线ADC

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-03-17 DOI: 10.1109/TVLSI.2025.3545364

Yabo Ni;Lu Liu;Yong Zhang;Tao Zhu

{"title":"A 12-bit 2-GS/s Pipeline ADC in 28-nm CMOS With Linear-Error Self-Calibration","authors":"Yabo Ni;Lu Liu;Yong Zhang;Tao Zhu","doi":"10.1109/TVLSI.2025.3545364","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3545364","url":null,"abstract":"This article discusses a 12-bit 2-GS/s pipeline analog-to-digital converter (ADC). A self-calibration technique is employed to correct linear errors due to capacitor mismatches and interstage gain errors (IGEs). To counteract the effects of power supply and temperature variations, the first three stages of the ADC are equipped with least-mean-squares (LMS) IGE background calibrations, enhanced by the injection of a 1-bit dither into these stages. The computational engines designed for background calibration were reused for self-calibration, simplifying the overall design. An improved integrated input buffer drives the ADC, achieving a bandwidth of approximately 6.3 GHz, which is essential for high-speed data acquisition and processing. Moreover, a low-power operational transconductance amplifier (OTA) and reference buffer, both operating on a 1.0-V supply, are implemented to minimize the chip’s power consumption. The 12-bit pipeline prototype ADC, fabricated using a 28-nm CMOS process, operates at 2-GS/s with a 1.0-Vpp input signal. It delivers a signal-to-noise-and-distortion ratio (SNDR) of 58.92 dB and a spurious-free dynamic range (SFDR) of 82.23 dB. The ADC core consumes only 180 mW, resulting in a Schreier figure of merits (FoMs) of 156.4 dB.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 6","pages":"1561-1569"},"PeriodicalIF":2.8,"publicationDate":"2025-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144117381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An RRAM Digital Computing-in-Memory Macro With Dual-Mode Multiplication and Maximum Value Rounding Adder Tree 具有双模乘法和最大值舍入加法树的RRAM数字内存计算宏

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-03-17 DOI: 10.1109/TVLSI.2025.3545866

Wang Ye;Hanghang Gao;Zhidao Zhou;Linfang Wang;Weizeng Li;Zhi Li;Jinshan Yue;Xiaoxin Xu;Jianguo Yang;Hongyang Hu;Chunmeng Dou

{"title":"An RRAM Digital Computing-in-Memory Macro With Dual-Mode Multiplication and Maximum Value Rounding Adder Tree","authors":"Wang Ye;Hanghang Gao;Zhidao Zhou;Linfang Wang;Weizeng Li;Zhi Li;Jinshan Yue;Xiaoxin Xu;Jianguo Yang;Hongyang Hu;Chunmeng Dou","doi":"10.1109/TVLSI.2025.3545866","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3545866","url":null,"abstract":"Implementing digital computing-in-memory (DCIM) based on resistive memory (RRAM) faces several critical challenges due to the small signal margin, large device variations, and large energy- and area-overhead induced by the digital adder tree (AT). To address these issues, we propose an RRAM DCIM macro based on the standard foundry one-transistor-one-resistor (1T1R) cell array featuring: 1) dual-mode MAC operation for efficiency- or accuracy-oriented optimization; 2) margin-enhanced digitized unit (MEDU) to amplify the signal ratio; and 3) maximum value rounding AT (MVR-AT) to reduce its power- and area-overhead. A test chip is demonstrated using a 180 nm CMOS process to verify the concept. It achieves a peak energy efficiency (EF) of 63.08 TOPS/W in the efficiency-oriented mode and a minimum error rate of 1.58% in the accuracy-oriented mode. Their combination can meet the requirements of different workloads in AI computing tasks to optimize the overall power consumption with negligible accuracy loss.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 6","pages":"1779-1783"},"PeriodicalIF":2.8,"publicationDate":"2025-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144117388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0