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IEEE Transactions on Very Large Scale Integration (VLSI) Systems最新文献

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Unrolled, Pipelined, and Stage-Folded Architectures for Encoding of Multi-Kernel Polar Codes 多内核极坐标编码的非卷积、流水线和分阶段折叠架构
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-14 DOI: 10.1109/tvlsi.2024.3436872
Hossein Rezaei, Elham Abbasi, Nandana Rajatheva, Matti Latva-Aho
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引用次数: 0
The Conjugated Current Mirrors: A General Enhancement in Transconductance Amplifiers 共轭电流镜：跨导放大器的全面提升
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-14 DOI: 10.1109/tvlsi.2024.3439525
Meysam Akbari, Kea-Tiong Tang
{"title":"The Conjugated Current Mirrors: A General Enhancement in Transconductance Amplifiers","authors":"Meysam Akbari, Kea-Tiong Tang","doi":"10.1109/tvlsi.2024.3439525","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3439525","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142194485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of Low-Complexity Quantized Compressive Sensing Using Measurement Predictive Coding 利用测量预测编码设计低复杂度量化压缩传感
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-12 DOI: 10.1109/tvlsi.2024.3438249
Lakshmi Bhanuprakash Reddy Konduru, Vikramkumar Pudi, Balasubramanyam Appina
{"title":"Design of Low-Complexity Quantized Compressive Sensing Using Measurement Predictive Coding","authors":"Lakshmi Bhanuprakash Reddy Konduru, Vikramkumar Pudi, Balasubramanyam Appina","doi":"10.1109/tvlsi.2024.3438249","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3438249","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142194486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
M2M: A Fine-Grained Mapping Framework to Accelerate Multiple DNNs on a Multi-Chiplet Architecture M2M： 在多芯片架构上加速多个 DNN 的细粒度映射框架
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-12 DOI: 10.1109/tvlsi.2024.3438549
Jinming Zhang, Xuyan Wang, Yaoyao Ye, Dongxu Lyu, Guojie Xiong, Ningyi Xu, Yong Lian, Guanghui He
{"title":"M2M: A Fine-Grained Mapping Framework to Accelerate Multiple DNNs on a Multi-Chiplet Architecture","authors":"Jinming Zhang, Xuyan Wang, Yaoyao Ye, Dongxu Lyu, Guojie Xiong, Ningyi Xu, Yong Lian, Guanghui He","doi":"10.1109/tvlsi.2024.3438549","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3438549","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142194489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
DLB-CNet: Difference Learning-Based Convolution Network for Building Change Detection DLB-CNet：用于建筑物变化检测的基于差分学习的卷积网络
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-09 DOI: 10.1109/tvlsi.2024.3438728
Zipeng Fan, Sanqian Wang, Xueting Pu, Yuting Cong, Yuan Liu, Xiubao Sui, Qian Chen
{"title":"DLB-CNet: Difference Learning-Based Convolution Network for Building Change Detection","authors":"Zipeng Fan, Sanqian Wang, Xueting Pu, Yuting Cong, Yuan Liu, Xiubao Sui, Qian Chen","doi":"10.1109/tvlsi.2024.3438728","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3438728","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141938986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 20-V Pulse Driver Based on All-nMOS Charge Pump Without Reversion Loss and Overstress in 65-nm Standard CMOS Technology 基于全 nMOS 充电泵的 20 V 脉冲驱动器，采用 65-nm 标准 CMOS 技术，无反向损耗和过应力
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-09 DOI: 10.1109/tvlsi.2024.3435974
Ziliang Zhou, Min Tan
{"title":"A 20-V Pulse Driver Based on All-nMOS Charge Pump Without Reversion Loss and Overstress in 65-nm Standard CMOS Technology","authors":"Ziliang Zhou, Min Tan","doi":"10.1109/tvlsi.2024.3435974","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3435974","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141939168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
RosebudVirt: A High-Performance and Partially Reconfigurable FPGA Virtualization Framework for Multitenant Networks RosebudVirt：面向多租户网络的高性能和部分可重构 FPGA 虚拟化框架
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-07 DOI: 10.1109/tvlsi.2024.3436017
Yiwei Chang, Zhichuan Guo
{"title":"RosebudVirt: A High-Performance and Partially Reconfigurable FPGA Virtualization Framework for Multitenant Networks","authors":"Yiwei Chang, Zhichuan Guo","doi":"10.1109/tvlsi.2024.3436017","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3436017","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141939170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Implementation of Reconfigurable Match Table for FPGA-Based Programmable Switches 基于 FPGA 的可编程开关的可重构匹配表的实现
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-07 DOI: 10.1109/tvlsi.2024.3436047
Xiaoyong Song, Zhichuan Guo
{"title":"An Implementation of Reconfigurable Match Table for FPGA-Based Programmable Switches","authors":"Xiaoyong Song, Zhichuan Guo","doi":"10.1109/tvlsi.2024.3436047","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3436047","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141939169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A High-Precision and High-Dynamic-Range Current-Mode WTA Circuit for Low-Supply-Voltage Applications 用于低电压应用的高精度、高动态范围电流模式 WTA 电路
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-07 DOI: 10.1109/tvlsi.2024.3436575
Mehdi Saberi, Hossein Yaghoobzadeh Shadmehri, Mohammad Tavakkoli Ghouchani, Alexandre Schmid
{"title":"A High-Precision and High-Dynamic-Range Current-Mode WTA Circuit for Low-Supply-Voltage Applications","authors":"Mehdi Saberi, Hossein Yaghoobzadeh Shadmehri, Mohammad Tavakkoli Ghouchani, Alexandre Schmid","doi":"10.1109/tvlsi.2024.3436575","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3436575","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141939171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Thresholding Decision-Directed Descent (T3D): A Tuning Solution for DDR5 DRAM DFEs 阈值决策定向下降 (T3D)：DDR5 DRAM DFE 的调整解决方案
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-06 DOI: 10.1109/tvlsi.2024.3435419
Mitchell Cooke, Nicola Nicolici
{"title":"Thresholding Decision-Directed Descent (T3D): A Tuning Solution for DDR5 DRAM DFEs","authors":"Mitchell Cooke, Nicola Nicolici","doi":"10.1109/tvlsi.2024.3435419","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3435419","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141938979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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