IEEE Transactions on Very Large Scale Integration (VLSI) Systems最新文献

{"title":"Processing-in-Memory Architecture for In-Storage Information Retrieval on 3-D NAND Flash Solid-State Drives","authors":"Huiwon Yun;Inho Jeong;Kyoyun Lee;Jaeyong Lee;Myoungjun Chun;Jihong Kim;Dongsuk Jeon","doi":"10.1109/TVLSI.2026.3692428","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3692428","url":null,"abstract":"Recent advances in retrieval-augmented generation (RAG) highlight retrieval latency, dominated by storage access, and large embedding-index size as the major bottlenecks. Although processing-in-memory (PIM) based on 3-D <sc>nand</small> flash and binary passage retriever (BPR) algorithm offer potential solutions for reducing latency and memory usage, naively integrating BPR algorithm into an SSD based on prior in-memory search (IMS) architectures results in negligible performance gain with substantial hardware overhead. This stems from the fact that prior IMS architectures are optimized only for search, leaving candidate readout misaligned with the <sc>nand</small> page direction and requiring excessive read cycles, while BPR's original top-<inline-formula> <tex-math>$L$ </tex-math></inline-formula> selection further requires high-precision ADCs and sorting logic. To address these limitations, we propose an algorithm–hardware co-designed in-storage information retrieval architecture. We introduce a hardware-efficient optimized BPR algorithm with a threshold-based selection and two-stage in-storage processing approach to minimize data transfer overheads. We further present an IMS architecture with page-aligned encoding that efficiently supports both search and candidate read operations, eliminating the read cycle penalty. We also present a lightweight in situ error monitoring scheme that bypasses error-correcting code (ECC) decoding while preserving error-aware refresh triggering. Experiments show that our design reduces the amount of data read from <sc>nand</small> flash by 7.94–<inline-formula> <tex-math>$1330.40times $ </tex-math></inline-formula> compared with host-side processing baselines and further reduces controller-to-host data transfer, while maintaining the retrieval accuracy. It also reduces total operation cycles by up to 96.93% compared with prior IMS architectures, and lowers error-detection power by 94.71% and total read energy by 17.22% compared with a conventional ECC decoder for error monitoring.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 8","pages":"2495-2508"},"PeriodicalIF":3.2,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148628309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Neuromorphic Hyperdimensional Computing for Efficiently Processing Event-Based Data","authors":"Tianyang Yu;Bi Wu;Ke Chen;Chenggang Yan;Gong Zhang;Weiqiang Liu","doi":"10.1109/TVLSI.2026.3695182","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3695182","url":null,"abstract":"The neuromorphic sensor’s event-based data output offers significant benefits, including minimal data redundancy and exceptional time resolution, which guarantee low power consumption and heightened sensitivity during the data acquisition process. Spiking neural network (SNN), with its inherent event-driven characteristic, is well-suited for processing event-based data, and its spike-based computing mechanism enhances the efficiency of data processing. Recent studies are exploring the integration of brain-inspired hyperdimensional computing (HDC) with SNN to leverage HDC’s advantages, including the low inference and training complexity, aiming to further reduce hardware overhead associated with SNN deployment. However, existing works have not effectively harnessed the information output by SNN during hyperdimensional encoding, leading to considerable area and energy overhead. In this article, an efficient neuromorphic HDC method is proposed, featuring a simplified hyperdimensional encoding approach that considers the temporal dynamics of SNN. In addition, a lightweight accelerator design matching the proposed method is also given. Experimental results show that the proposed accelerator achieves over 50% area reduction and reduces energy consumption by 20%–90%.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 8","pages":"2483-2494"},"PeriodicalIF":3.2,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148626313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A High-Efficiency Optimization Design Method for ADC System Under Multiple PVT Conditions via Transfer Learning","authors":"Yunqi Yang;Jiaming Su;Dongdong Chen;Di Li;Yintang Yang","doi":"10.1109/TVLSI.2026.3692184","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3692184","url":null,"abstract":"The design for the analog-to-digital converter (ADC) system relies heavily on manual experience, and the performance is sensitive to variations in the external environment. In this research, a high-efficiency optimization design method via transfer learning (TL) is proposed. High-accuracy convolutional neural network (CNN)-IC models are trained to describe the relationship between design parameters and performance metrics. Based on the extracted circuit features by CNN-IC models, a transfer scheme is proposed to establish high-accuracy CNN-IC models under different process, voltage, and temperature (PVT) conditions with few-shot samples. The fitting accuracy (R<inline-formula> <tex-math>${}^{2}$ </tex-math></inline-formula>) of all the transferred models can reach over 99%, and the required amount of data is 10% of the original data. An optimization function is established, which contains the performance metrics and PVT design specifications. Then, the constrained particle swarm optimization (PSO) algorithm is adopted to efficiently optimize the design parameters considering multiple PVT conditions. Three key circuits in the ADC system, including a two-stage Miller-compensated operational amplifier (TSMCOA), bandgap reference (BGR), and successive approximation register (SAR) ADC circuits, are selected to be optimized. The optimized running times of the above three circuits are only 215, 341, and 549 s, respectively. The optimized power consumptions (PCs) are <inline-formula> <tex-math>$56.22~mu $ </tex-math></inline-formula>W, <inline-formula> <tex-math>$159~mu $ </tex-math></inline-formula>W, and 1.45 mW, respectively, while all performance metrics can meet the design specifications under different PVT conditions. Compared with the advanced model-based methods, the training data can be decreased by at least <inline-formula> <tex-math>$2.3times $ </tex-math></inline-formula>, <inline-formula> <tex-math>$3times $ </tex-math></inline-formula>, and <inline-formula> <tex-math>$3times $ </tex-math></inline-formula>, respectively. Thus, the proposed method can effectively decrease the simulation cost and accelerate the design process.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 8","pages":"2344-2354"},"PeriodicalIF":3.2,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148627018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information","authors":"","doi":"10.1109/TVLSI.2026.3708946","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3708946","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 8","pages":"C3-C3"},"PeriodicalIF":3.2,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11626107","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148627030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fused-STA: Automated Design Space Exploration of a Fused Systolic Tensor Array for Universal Deep Learning Acceleration","authors":"Jooyeon Lee;Sangwoo Jung;Jaeha Kung","doi":"10.1109/TVLSI.2026.3693713","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3693713","url":null,"abstract":"Systolic array architectures have become the dominant solution for accelerating deep neural network (DNN) computations, yet designing optimal configurations remains challenging due to the vast design space spanning array dimensions, dataflow strategies, SRAM allocations, and tiling sizes. Existing tool-aided optimization frameworks constrain this design space by treating SRAM sizes or tiling sizes as fixed input parameters, while focusing only on conventional systolic arrays, limiting their ability to discover a truly optimal design. This article presents a comprehensive framework for systolic tensor array (STA) design space exploration that jointly optimizes array configurations, SRAM sizes, tiling sizes, and dataflow types. We introduce TensorSim, a cycle-accurate simulator with an ML-based synthesis prediction model, and TensorOptimizer, an automated multiobjective optimization framework. Evaluation with TensorOptimizer across 12 representative DNNs—from edge-level convolutional neural networks (CNNs) to billion-parameter large language models (LLMs)—reveals that output stationary (OS) dataflows outperform weight stationary (WS) dataflows by <inline-formula> <tex-math>$1.53times $ </tex-math></inline-formula> on edge workloads, while WS achieves <inline-formula> <tex-math>$2.13times $ </tex-math></inline-formula> higher efficiency over OS on server-scale computations. Based on these insights, we propose Fused-STA, a reconfigurable architecture that dynamically switches between OS and WS modes within a unified hardware substrate. Fused-STA achieves over 91% of the oracle single-dataflow performance, specifically designed for a single network, providing <inline-formula> <tex-math>$2.34times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$1.92times $ </tex-math></inline-formula> improvements over a tensor processing unit (TPU)-like baseline on edge-level and server-level benchmarks, respectively.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 8","pages":"2355-2368"},"PeriodicalIF":3.2,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148626222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Efficient Hardware Accelerator for CKKS En/Decoding and En/Decryption With Dynamic Twiddle Factor Generation","authors":"Pengfei Sun;Makoto Ikeda","doi":"10.1109/TVLSI.2026.3695913","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3695913","url":null,"abstract":"Homomorphic encryption (HE), including Cheon– Kim–Kim–Song (CKKS), enables secure cloud computation over encrypted data. While prior work predominantly accelerates cloud-side evaluation, the client-side remains a critical and underexplored bottleneck. This article presents a dedicated hardware accelerator for client-side CKKS preparation. Specifically, we make three key contributions: a unified multiplier architecture that supports both number theoretic transform (NTT) and fast Fourier transform (FFT) to avoid logic duplication and reduce area; an in-place memory organization with relaxed layout constraints to improve data reuse and lower on-chip storage overhead; and a dynamic twiddle factor (TF) generator that removes large prestored constant tables while preserving low-latency. The proposed design efficiently implements CKKS encoding, encryption, decryption, and decoding, enabling low-latency secure interactions. Evaluation on TSMC 28-nm ASIC and Xilinx UltraScale+ FPGA shows over 40% reduction in area/gate count compared with representative hardware baselines and a <inline-formula> <tex-math>$1.2times $ </tex-math></inline-formula> end-to-end speedup for client-side CKKS operations, demonstrating the design’s practicality for efficient homomorphic data preparation.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 8","pages":"2434-2444"},"PeriodicalIF":3.2,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148626430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Balancing FP8 Computation Accuracy and Efficiency on Digital CIM via Shift-Aware On-the-Fly Aligned-Mantissa Bitwidth Prediction","authors":"Liang Zhao;Kunming Shao;Zhipeng Liao;Xijie Huang;Tim Kwang-Ting Cheng;Chi-Ying Tsui;Yi Zou","doi":"10.1109/TVLSI.2026.3693970","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3693970","url":null,"abstract":"FP8 low-precision formats have gained significant adoption in transformer inference and training. However, existing digital compute-in-memory (DCIM) architectures face challenges in supporting variable FP8 aligned-mantissa bitwidths, as unified alignment strategies and fixed-precision multiply accumulate (MAC) units struggle to handle input data with diverse distributions. This work presents a flexible FP8 DCIM accelerator with three innovations: 1) a dynamic shift-aware bitwidth prediction (DSBP) with on-the-fly input prediction that adaptively adjusts weight (2/4/6/8b) and input (<inline-formula> <tex-math>$2sim 12$ </tex-math></inline-formula>b) aligned-mantissa precision; 2) a FIFO-based input alignment unit (FIAU) replacing complex barrel shifters with pointer-based control; and 3) a precision-scalable INT MAC array achieving flexible weight precision with minimal overhead. Implemented in 28-nm CMOS with a <inline-formula> <tex-math>$64~times ~96$ </tex-math></inline-formula> CIM array, the design achieves 20.4 TFLOPS/W for fixed E5M7, demonstrating <inline-formula> <tex-math>$2.8times $ </tex-math></inline-formula> higher FP8 efficiency than previous work while supporting all FP8 formats. Results on Llama-7b show that the DSBP achieves higher efficiency than fixed bitwidth mode at the same accuracy level on both BoolQ and Winogrande datasets, with configurable parameters enabling flexible accuracy–efficiency tradeoffs.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 8","pages":"2671-2675"},"PeriodicalIF":3.2,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148627026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reconfigurable In-Memory Computing With Compute-Fusion SAR ADC for Area-Efficient Pipelined MAC Operations","authors":"S. Q. Yan;J. J. Wang;S. Liu;Y. T. Liu;Y. Wang;Z. Q. Wu;H. D. Mao;X. Z. Wang;T. P. Chen;Y. Liu","doi":"10.1109/TVLSI.2026.3689104","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3689104","url":null,"abstract":"This brief proposes a reconfigurable compute-in-memory (CIM) macro using a compute-fusion successive approximation register ADC (CF-SAR) that integrates charge-domain multiply-and-accumulate (MAC), SAR quantization, and partial-sum accumulation in a unified data path. By reusing the capacitor array for both analog MAC and ADC conversion, the design reduces area overhead. A reconfigurable in-memory-computing storage and logic (RSL) element merges SAR result storage with in-memory serial addition (IMSA), enabling a pipelined ping-pong quantization/serial accumulation scheme without external digital adders. The macro supports 1-/2-/4-bit signed and unsigned weights via <sc>and</small>/<sc>nand</small> selection and bank swapping without extra hardware. Implemented in 40 nm CMOS, the macro reduces transistor count by 44%, achieving up to 250.73 TOPS/W and 255.5 GOPS, with normalized efficiencies of 273.92 TOPS/W and 197.61 TOPS/mm², and 98.54%/86.62% accuracy on MNIST/CIFAR-10.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 8","pages":"2636-2640"},"PeriodicalIF":3.2,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148627540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of Random Forest-Based Low-Power VLSI Architecture to Detect Congestive Heart Failure for Wearable Devices","authors":"Abhyuday Bhardwaj;Meenali Janveja;Srinivasan Krishnaswamy;Jan Pidanic;Gaurav Trivedi","doi":"10.1109/TVLSI.2026.3697012","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3697012","url":null,"abstract":"Congestive heart failure (CHF) is an acute syndrome that results from ventricular dysfunction and progresses in four stages. Its timely detection can reverse heart damage and save lives. This work proposes a low-power, computationally efficient VLSI architecture to detect CHF using a single-lead ECG signal for the first time. This architecture employs a novel wavelet function-based electrocardiogram (ECG) feature extraction method and a random forest (RF) classifier, which can classify regular beats from CHF beats using a subject-oriented approach. Using ECG signals from publicly available datasets, BIDMC-CHF and MIT-BIH NSRDB, the proposed architecture achieves 90.5% accuracy, having a power consumption of <inline-formula> <tex-math>$0.1~mu W$ </tex-math></inline-formula> when implemented using TSMC 40-nm bulk CMOS technology as an ASIC. The low power consumption of the proposed architecture enables it to be utilized efficiently for real-time ECG analysis in wearable devices.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 8","pages":"2445-2456"},"PeriodicalIF":3.2,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148627770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Rethinking Area Optimization for High-Throughput Hardware Accelerator of Number Theoretic Transform: A Case Study on ML-KEM","authors":"Hao Luo;Minghao Li;Suwen Song;Zhongfeng Wang","doi":"10.1109/TVLSI.2026.3697390","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3697390","url":null,"abstract":"The computation-intensive modular multiplications in number theoretic transform (NTT) present significant bottlenecks for lattice-based post-quantum cryptography (PQC). In this article, we propose a systematic area optimization strategy through joint algorithm-hardware codesign. First, we propose two high-throughput architectures to accommodate diverse throughput requirements: a fully parallel NTT and a folded 64-point variant derived from the former, which both feature area-efficient constant modular multipliers. A novel permutation-based algorithm is developed to reuse the NTT architecture for inverse NTT without structural modifications. Second, an area-driven, automated decomposition-based design strategy for constant modular multipliers is developed to reduce hardware overhead. The strategy involves a three-stage process: decomposing, analyzing, and selecting, which are based on finite-field properties and comprehensive circuit modeling. Finally, the proposed architectures are evaluated on Artix-7 AC701 FPGA with the parameters of the module-lattice-Based key-encapsulation mechanism (ML-KEM) from the latest PQC standard. The results show that the optimized modular multipliers deliver an average resource reduction of approximately 46% over the prior art. Furthermore, operating at 189 MHz, the core throughputs reach 47.2 and <inline-formula> <tex-math>$94.5times 10^{6}$ </tex-math></inline-formula> operations per second (OPS) for the proposed folded and fully parallel structures, respectively, while both architectures achieve an I/O-limited throughput of <inline-formula> <tex-math>$23.6{,}times{,}10^{6}$ </tex-math></inline-formula> OPS. Compared to the state-of-the-art highly parallel designs, our work provides a 31.1% area efficiency improvement.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 8","pages":"2457-2468"},"PeriodicalIF":3.2,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148627793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}