IEEE Transactions on Very Large Scale Integration (VLSI) Systems最新文献_第3页

Unveiling the True Power of the Latched Ring Oscillator for a Unified PUF and TRNG Architecture 揭示用于统一 PUF 和 TRNG 架构的锁相环振荡器的真正威力

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-09-04 DOI: 10.1109/tvlsi.2024.3448503

Riccardo Della Sala, Davide Bellizia, Giuseppe Scotti

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ReAdapt-II: Energy-Quality Optimizations for VLSI Adaptive Filters Through Automatic Reconfiguration and Built-In Iterative Dividers ReAdapt-II：通过自动重新配置和内置迭代除法器优化 VLSI 自适应滤波器的能耗质量

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-09-04 DOI: 10.1109/tvlsi.2024.3446235

Pedro T. L. Pereira, Patrícia Ucker L. Costa, Eduardo da Costa, Paulo Flores, Sergio Bampi

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A Second-Order Noise Shaping SAR ADC With Parallel Multiresidual Integrator 带并行多冗余积分器的二阶噪声整形 SAR ADC

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-30 DOI: 10.1109/TVLSI.2024.3447740

Yang Zhou;Wenjie Wang;Longbin Zhu;Zhengtao Zhu;Risheng Su;Jianan Zheng;Siyuan Xie;Jihong Li;Fanyi Meng;Zhijun Zhou;Keping Wang

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A 0.05–1.5-GHz PVT-Insensitive Digital-to-Time Converter for QKD Applications 用于 QKD 应用的 0.05-1.5 GHz PVT 不敏感数时转换器

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-30 DOI: 10.1109/tvlsi.2024.3447111

Haiyue Yan, Yan Ye, Wenjia Li, Xuefei Bai

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Power-Efficient Analog Hardware Architecture of the Learning Vector Quantization Algorithm for Brain Tumor Classification 用于脑肿瘤分类的学习矢量量化算法的高能效模拟硬件架构

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-30 DOI: 10.1109/TVLSI.2024.3447903

Vassilis Alimisis;Emmanouil Anastasios Serlis;Andreas Papathanasiou;Nikolaos P. Eleftheriou;Paul P. Sotiriadis

{"title":"Power-Efficient Analog Hardware Architecture of the Learning Vector Quantization Algorithm for Brain Tumor Classification","authors":"Vassilis Alimisis;Emmanouil Anastasios Serlis;Andreas Papathanasiou;Nikolaos P. Eleftheriou;Paul P. Sotiriadis","doi":"10.1109/TVLSI.2024.3447903","DOIUrl":"10.1109/TVLSI.2024.3447903","url":null,"abstract":"This study introduces a design methodology pertaining to analog hardware architecture for the implementation of the learning vector quantization (LVQ) algorithm. It consists of three main approaches that are separated based on the distance calculation circuit (DCC) and, more specifically; Euclidean distance, Sigmoid function, and Squarer circuits. The main building blocks of each approach are the DCC and the current comparator (CC). The operational principles of the architecture are extensively elucidated and put into practice through a power-efficient configuration (operating less than 650 nW) within a low-voltage setup (0.6 V). Each specific implementation is tested on a brain tumor classification task achieving more than 96.00% classification accuracy. The designs are realized using a 90-nm CMOS process and developed utilizing the Cadence IC Suite for both schematic and physical design. Through a comparative analysis of postlayout simulation outcomes with an equivalent software-based classifier and related works, the accuracy of the applied modeling and design methodologies is validated.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142194475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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HPR-Mul: An Area and Energy-Efficient High-Precision Redundancy Multiplier by Approximate Computing HPR-Mul：通过近似计算实现面积和能效的高精度冗余乘法器

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-29 DOI: 10.1109/TVLSI.2024.3445108

Jafar Vafaei;Omid Akbari

{"title":"HPR-Mul: An Area and Energy-Efficient High-Precision Redundancy Multiplier by Approximate Computing","authors":"Jafar Vafaei;Omid Akbari","doi":"10.1109/TVLSI.2024.3445108","DOIUrl":"10.1109/TVLSI.2024.3445108","url":null,"abstract":"For critical applications that require a higher level of reliability, the triple modular redundancy (TMR) scheme is usually employed to implement fault-tolerant arithmetic units. However, this method imposes a significant area and power/energy overhead. Also, the majority-based voter in the typical TMR designs is highly sensitive to soft errors and the design diversity of the triplicated module, which may result in an error for a small difference between the output of the TMR modules. However, a wide range of applications deployed in critical systems are inherently error-resilient, that is, they can tolerate some inexact results at their output while having a given level of reliability. In this article, we propose a high precision redundancy multiplier (HPR-Mul) that relies on the principles of approximate computing to achieve higher energy efficiency and lower area, as well as resolve the aforementioned challenges of the typical TMR schemes, while retaining the required level of reliability. The HPR-Mul is composed of full precision (FP) and two reduced precision (RP) multipliers, along with a simple voter to determine the output. Unlike the state-of-the-art RP redundancy multipliers (RPR-Muls) that require a complex voter, the voter of the proposed HPR-Mul is designed based on mathematical formulas resulting in a simpler structure. Furthermore, we use the intermediate signals of the FP multiplier as the inputs of the RP multipliers, which significantly enhance the accuracy of the HPR-Mul. The efficiency of the proposed HPR-Mul is evaluated in a 15-nm FinFET technology, where the results show up to 70% and 69% lower power consumption and area, respectively, compared to the typical TMR-based multipliers. Also, the HPR-Mul outperforms the state-of-the-art RPR-Mul by achieving up to 84% higher soft error tolerance. Moreover, by employing the HPR-Mul in different image processing applications, up to 13% higher output image quality is achieved in comparison with the state-of-the-art RPR multipliers.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142194479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A CMOS Readout Circuit for Resistive Tactile Sensor Array Using Crosstalk Suppression and Nonuniformity Compensation Techniques 采用串音抑制和不均匀性补偿技术的电阻式触觉传感器阵列 CMOS 读出电路

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-27 DOI: 10.1109/tvlsi.2024.3447164

Yao Li, Junfeng Geng, Mao Ye, Jiaji He, Xiaoxiao Zheng, Qiuwei Wang, Yiqiang Zhao

引用次数: 0

Spread Spectrum-Based Countermeasures for Cryptographic RISC-V SoC 基于扩频的密码 RISC-V SoC 对策

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-27 DOI: 10.1109/tvlsi.2024.3444851

Thai-Ha Tran, Ba-Anh Dao, Duc-Hung Le, Van-Phuc Hoang, Trong-Thuc Hoang, Cong-Kha Pham

引用次数: 0

Detect and Replace: Efficient Soft Error Protection of FPGA-Based CNN Accelerators 检测和替换：基于 FPGA 的 CNN 加速器的高效软错误保护

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-26 DOI: 10.1109/tvlsi.2024.3443834

Zhen Gao, Yanmao Qi, Jinchang Shi, Qiang Liu, Guangjun Ge, Yu Wang, Pedro Reviriego

引用次数: 0

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information IEEE 超大规模集成 (VLSI) 系统论文集出版信息

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-26 DOI: 10.1109/TVLSI.2024.3422690

引用次数: 0