Enhancing Memory BIST With an Optimized RTL-BIST IP Core: A Low-Power, High-Fault-Coverage Approach

IF 3.1 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-06-27 DOI:10.1109/TVLSI.2025.3581296

Ming-Yi Lin;Wei-Kuan Chiang;Chin-Hung Wang

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引用次数: 0

Abstract

The increasing density of static random access memory (SRAM) in modern system-on-chip (SoC) architectures has intensified the need for efficient built-in self-test (BIST) solutions to ensure fault detection and repair. This article presents an optimized register transfer level (RTL)-BIST intellectual property core (IP core) that integrates a novel March mSR+ algorithm, providing a low-power, high-fault-coverage approach to embedded memory testing. Developed using high-level synthesis (HLS), the proposed framework enhances test efficiency while minimizing hardware complexity. Experimental results on field-programmable gate array (FPGA) implementations demonstrate that the March mSR+ algorithm achieves an 88.89% fault coverage while reducing power consumption compared with conventional March-based testing methods. These findings validate the effectiveness of the RTL-BIST framework in improving memory reliability for artificial intelligence (AI), high-performance computing (HPC), and safety-critical applications.

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用优化的RTL-BIST IP核增强内存BIST：一种低功耗、高故障覆盖率的方法

在现代片上系统（SoC）架构中，静态随机存取存储器（SRAM）的密度不断增加，这增加了对高效内置自检（BIST）解决方案的需求，以确保故障检测和修复。本文提出了一种优化的寄存器传输电平(RTL)-BIST知识产权核（IP核），它集成了一种新颖的March mSR+算法，为嵌入式内存测试提供了一种低功耗、高故障覆盖率的方法。使用高级综合（HLS）开发的框架提高了测试效率，同时最小化了硬件复杂性。在现场可编程门阵列（FPGA）上的实验结果表明，与传统的基于March的测试方法相比，March mSR+算法的故障覆盖率达到了88.89%，同时降低了功耗。这些发现验证了RTL-BIST框架在提高人工智能（AI）、高性能计算（HPC）和安全关键应用的内存可靠性方面的有效性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.