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IEEE Transactions on Very Large Scale Integration (VLSI) Systems最新文献

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High-Performance Error and Erasure Decoding With Low Complexities Using SPC-RS Concatenated Codes 利用 SPC-RS 连接编码实现低复杂度的高性能纠错和擦除解码
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-06 DOI: 10.1109/tvlsi.2024.3435773
Zhihao Zhou, Wei Zhang, Xinyi Guo, Jianhan Zhao, Yanyan Liu
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引用次数: 0
Low-Jitter Frequency Doubling Circuit Supporting Higher-Speed BISG and Aging Sensing in a Chiplet-Based Design Environment 基于 Chiplet 的设计环境中支持更高速 BISG 和老化传感的低抖动倍频电路
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-05 DOI: 10.1109/tvlsi.2024.3435059
Ko-Hong Lin, Ont-Derh Lin, Shi-Yu Huang, Duo Sheng
{"title":"Low-Jitter Frequency Doubling Circuit Supporting Higher-Speed BISG and Aging Sensing in a Chiplet-Based Design Environment","authors":"Ko-Hong Lin, Ont-Derh Lin, Shi-Yu Huang, Duo Sheng","doi":"10.1109/tvlsi.2024.3435059","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3435059","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141939172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A High-Speed Dynamic Element Matching Decoder With Integrated Background Calibration Control 集成背景校准控制的高速动态元素匹配解码器
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-07-30 DOI: 10.1109/tvlsi.2024.3432640
Tobias Schirmer, Simon Buhr, Felix Burkhardt, Florian Protze, Frank Ellinger
{"title":"A High-Speed Dynamic Element Matching Decoder With Integrated Background Calibration Control","authors":"Tobias Schirmer, Simon Buhr, Felix Burkhardt, Florian Protze, Frank Ellinger","doi":"10.1109/tvlsi.2024.3432640","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3432640","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141867464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Efficient Two-Stage Pipelined Compute-in-Memory Macro for Accelerating Transformer Feed-Forward Networks 用于加速变压器前馈网络的高效两级流水线内存计算宏程序
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-07-29 DOI: 10.1109/tvlsi.2024.3432403
Heng Zhang, Wenhe Yin, Sunan He, Yuan Du, Li Du
{"title":"An Efficient Two-Stage Pipelined Compute-in-Memory Macro for Accelerating Transformer Feed-Forward Networks","authors":"Heng Zhang, Wenhe Yin, Sunan He, Yuan Du, Li Du","doi":"10.1109/tvlsi.2024.3432403","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3432403","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141867412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Low-Cost Quadruple-Node-Upsets Resilient Latch Design 低成本四重节点镦粗弹性锁存器设计
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-07-29 DOI: 10.1109/tvlsi.2024.3430224
Luchang He, Chenchen Xie, Qingyu Wu, Siqiu Xu, Houpeng Chen, Xing Ding, Xi Li, Zhitang Song
{"title":"A Low-Cost Quadruple-Node-Upsets Resilient Latch Design","authors":"Luchang He, Chenchen Xie, Qingyu Wu, Siqiu Xu, Houpeng Chen, Xing Ding, Xi Li, Zhitang Song","doi":"10.1109/tvlsi.2024.3430224","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3430224","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141867465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Electrical–Thermal Co-Simulation Model of Chiplet Heterogeneous Integration Systems 芯片组异构集成系统的电热协同仿真模型
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-07-29 DOI: 10.1109/tvlsi.2024.3430498
Xiaoning Ma, Qinzhi Xu, Chenghan Wang, He Cao, Jianyun Liu, Daoqing Zhang, Zhiqiang Li
{"title":"An Electrical–Thermal Co-Simulation Model of Chiplet Heterogeneous Integration Systems","authors":"Xiaoning Ma, Qinzhi Xu, Chenghan Wang, He Cao, Jianyun Liu, Daoqing Zhang, Zhiqiang Li","doi":"10.1109/tvlsi.2024.3430498","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3430498","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141867469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 370-nW Bio-AFE With 2.9-$mu$Vrms Input Noise in an Octa-Channel System-in-Package for Multimode Bio-Signal Acquisition 用于多模生物信号采集的八通道系统级封装中的 370-nW Bio-AFE，输入噪声为 2.9 美元/毫微伏
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-07-29 DOI: 10.1109/tvlsi.2024.3430059
Patrick Fath, Harald Pretl
{"title":"A 370-nW Bio-AFE With 2.9-$mu$Vrms Input Noise in an Octa-Channel System-in-Package for Multimode Bio-Signal Acquisition","authors":"Patrick Fath, Harald Pretl","doi":"10.1109/tvlsi.2024.3430059","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3430059","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141867467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information 电气和电子工程师学会超大规模集成 (VLSI) 系统学会论文集信息
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-07-25 DOI: 10.1109/TVLSI.2024.3418151
{"title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information","authors":"","doi":"10.1109/TVLSI.2024.3418151","DOIUrl":"10.1109/TVLSI.2024.3418151","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10609532","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141780234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and Analysis of a New Three-Stage Feedback Amplifier Utilizing Signal Flow Graph Domain Inspection Approach 利用信号流图域检测法设计和分析新型三级反馈放大器
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-07-25 DOI: 10.1109/tvlsi.2024.3426516
M. Ghashghai, M. B. Ghaznavi-Ghoushchi
{"title":"Design and Analysis of a New Three-Stage Feedback Amplifier Utilizing Signal Flow Graph Domain Inspection Approach","authors":"M. Ghashghai, M. B. Ghaznavi-Ghoushchi","doi":"10.1109/tvlsi.2024.3426516","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3426516","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141780232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of Octave Tuning Range $LC$ VCO With Ultralow $K_{text{VCO}}$ Using Frequency-Dependent Implicit Capacitance Neutralization Technique 利用频率相关隐含电容中和技术设计具有超低 $K_{text{VCO}}$ 的倍频程调谐范围 $LC$ VCO
IF 2.8 2区 工程技术
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-07-25 DOI: 10.1109/tvlsi.2024.3430544
Youming Zhang, Xusheng Tang, Tonglu Jiao, Peng Liu, Jingchen Liu
{"title":"Design of Octave Tuning Range $LC$ VCO With Ultralow $K_{text{VCO}}$ Using Frequency-Dependent Implicit Capacitance Neutralization Technique","authors":"Youming Zhang, Xusheng Tang, Tonglu Jiao, Peng Liu, Jingchen Liu","doi":"10.1109/tvlsi.2024.3430544","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3430544","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141780233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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