IEEE Transactions on Very Large Scale Integration (VLSI) Systems最新文献

{"title":"Right-Sized Security: Configurable Security Engine for Supply-Chain Integrity in Resource-Constrained System-on-Chip Designs","authors":"Tambiara Tabassum;Emmanuel Elias;Kshitij Raj;Atri Chatterjee;Swarup Bhunia;Sandip Ray","doi":"10.1109/TVLSI.2026.3693611","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3693611","url":null,"abstract":"Modern system-on-chip (SoC) designs are increasingly vulnerable to supply chain threats such as counterfeiting, overproduction, and reverse engineering, leading to financial losses, intellectual property (IP) theft, and compromised system integrity. Existing security engines, while effective in principle, typically rely on microcontroller-based architectures that incur significant area and power overhead, making them impractical for resource-constrained devices. In this article, we present a minimally configured security engine (MCSE), a lightweight, modular, configurable security engine designed to address the most critical supply-chain threats with minimal resource consumption. We introduce the notion of <italic>minimum security</i>, a baseline set of protection features necessary to secure SoCs under strict area and power constraints, and demonstrate how MCSE can be tailored to meet diverse system requirements. We validate our architecture through implementation on multiple ASIC technology nodes, showing favorable tradeoffs between security capability, area, and power. Our results establish MCSE as a compelling solution for integrating supply chain protection into low-power and area-sensitive SoC designs.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 8","pages":"2571-2581"},"PeriodicalIF":3.2,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148628346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low-Area and High-Speed 10-Transistor/Bit Incrementers and Decrementers With Group-Carry Generation","authors":"Min-Woo Kim;Byung-Do Yang","doi":"10.1109/TVLSI.2026.3687943","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3687943","url":null,"abstract":"This brief proposes low-area and high-speed 10-transistor/bit incrementers and decrementers with group-carry (GC) generation. The low-area incrementer (LA-INC) and low-area decrementer (LA-DEC) circuits modify the conventional half-adder (HA) based circuits. In 1-bit increment and decrement circuits, the number of transistors reduces from 12 to 10, and the carry-path delays are reduced to one gate delay (<sc>nand</small> or <sc>nor</small> gate) from two gate delays (<sc>and</small> or <sc>or</small> gate). <inline-formula> <tex-math>$N$ </tex-math></inline-formula>-bit LA-INC and LA-DEC use the conventional ripple carry structure. They have <inline-formula> <tex-math>$10N -12$ </tex-math></inline-formula> transistors and <inline-formula> <tex-math>$N -1$ </tex-math></inline-formula> gate delay. The proposed high-speed incrementer (HS-INC) and high-speed decrementer (HS-DEC) circuits further reduce their carry-path delays by using the GC generation. In this design, <inline-formula> <tex-math>$N~1$ </tex-math></inline-formula>-bit incrementers and decrementers are grouped to <inline-formula> <tex-math>$N$ </tex-math></inline-formula>/4 4-bit incrementers and decrementers for high-speed operations. The number of bits for each incrementer group can be adjusted by considering the delay. 16-bit increment and decrement are implemented with a 1.2 V 65 nm CMOS process. The LA-INC, LA-DEC, HS-INC, and HS-DEC circuits reduce the delay and power to 47%–56% and 21%–26% compared to the HA-based circuits, respectively.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 8","pages":"2626-2630"},"PeriodicalIF":3.2,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148626229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Toward Efficient Edge AI With Heterogeneous Computing and Multilevel Optimization","authors":"Jingyuan Li;Xinyu Cai;Yuan Dai;Wenbo Yin;Lingli Wang","doi":"10.1109/TVLSI.2026.3697086","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3697086","url":null,"abstract":"The rapid progress of artificial intelligence (AI) has brought increasing demands on hardware accelerators, particularly as modern models combine dense linear operations with a growing number of irregular, nonlinear, and control-intensive operators. While tensor cores and systolic arrays offer high throughput for regular computations, they often struggle to efficiently support the diverse operations emerging in recent model structures. Coarse-grained reconfigurable arrays (CGRAs), with their spatial parallelism and reconfigurability, may serve as a natural complement to dense accelerators in such heterogeneous workloads. In this work, we propose EUREKA, a heterogeneous acceleration framework that integrates tensor cores with CGRAs through a unified instruction set, cross-architecture data scheduling, tailored hardware support for nonlinear operators, and optimizations at the instruction, task, and operator levels to exploit parallelism. At the software level, we introduce a hierarchical compilation strategy that combines graph-level optimizations with tensor-level scheduling techniques. To address the large design space of hardware–software co-optimization, we further develop a Bayesian optimization-based exploration scheme enhanced with kernel compression methods, which provides an efficient means of identifying promising hardware configurations and scheduling strategies. Experiment results on representative AI benchmarks show that EUREKA improves execution efficiency, achieving an average <inline-formula> <tex-math>$12.6times $ </tex-math></inline-formula> normalized performance gain over state-of-the-art frameworks.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 8","pages":"2383-2396"},"PeriodicalIF":3.2,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148626393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 3.2-GHz Ring-Oscillator-Based Charge-Pump PLL With Time-Domain Optimization of PFD Reset Delay","authors":"Seunghoon Yi;Hee-Cheol Joo;Yoochang Kim;Young-Ha Hwang","doi":"10.1109/TVLSI.2026.3690678","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3690678","url":null,"abstract":"This brief presents a time-domain method to optimize the phase-frequency detector (PFD) reset delay, <inline-formula> <tex-math>$tau _{reset}$ </tex-math></inline-formula>, in charge-pump (CP) phase-locked loops (PLLs). In charge-pump PLLs (CP-PLLs), reducing <inline-formula> <tex-math>$tau _{reset}$ </tex-math></inline-formula> generally lowers the reference spur and can improve jitter, but an excessively small <inline-formula> <tex-math>$tau _{reset}$ </tex-math></inline-formula> causes the PFD dead-zone operation and degrades jitter. To narrow <inline-formula> <tex-math>$tau _{reset}$ </tex-math></inline-formula> search space and identify its optimum, the proposed method uses a SystemVerilog (SV)-based PFD-CP behavioral model that represents current settling, charge sharing, charge injection, and clock feedthrough using piecewise exponential functions to reproduce the CP output-current waveform. Compared with a conventional phase-domain model, the proposed model predicts <inline-formula> <tex-math>$tau _{reset}$ </tex-math></inline-formula>-dependent PLL behavior more accurately. At <inline-formula> <tex-math>$tau _{reset} = 100$ </tex-math></inline-formula> ps, the jitter prediction error is reduced from 66.7% to 8.7%. In addition, the proposed reference-spur-based <inline-formula> <tex-math>$tau _{reset}$ </tex-math></inline-formula> selection identifies the same optimum <inline-formula> <tex-math>$tau _{reset}$ </tex-math></inline-formula> as the postlayout simulation. A 3.2-GHz prototype CP-PLL fabricated in 28-nm CMOS validates the proposed method and, at the optimized <inline-formula> <tex-math>$tau _{reset}$ </tex-math></inline-formula>, achieves an rms jitter of 1.12 ps, a reference spur of −56.4 dBc, a power efficiency of 1.09 mW/GHz, and an FoM<inline-formula> <tex-math>${}_{J}$ </tex-math></inline-formula> of −233.6 dB.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 8","pages":"2651-2655"},"PeriodicalIF":3.2,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148627541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"RMC PUF: A Highly Reliable PUF Architecture Based on Recursive Markov Chain Obfuscation","authors":"Zhengfeng Huang;Zhao Yang;Xuxiang Sun;Yingchun Lu;Jingchang Bian;Yiming Ouyang;Tianming Ni;Xiaoqing Wen","doi":"10.1109/TVLSI.2026.3693479","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3693479","url":null,"abstract":"Physical unclonable functions (PUFs) are critical hardware security primitives that extract entropy from intrinsic manufacturing process variations (MPVs) to generate unique cryptographic responses. They have demonstrated extensive application prospects in lightweight encryption and authentication for Internet of Things (IoT) devices. However, the classic arbiter PUF (APUF) is inherently vulnerable to machine learning (ML) modeling attacks due to the linear mathematical model of its delay circuits. To address this challenge, this article proposes a novel postprocessing obfuscation architecture named recursive Markov chain PUF (RMC PUF). The proposed architecture couples an APUF core with Markov obfuscation modules. By exploiting the intermediate stage responses of the APUF as an entropy source, the system constructs a 1-D recursive stochastic state transition mechanism. This approach recursively transforms and obfuscates the raw entropy based on Markov Chain theory, achieving a PUF system with stability and robust resistance against ML attacks. Through this efficient recursive obfuscation strategy, the design achieves precise utilization of the APUF’s intrinsic entropy. The work is validated through both numerical simulation and FPGA prototyping. Experimental results show that the prototype maintains a high reliability of 98.9%–99.9% within a voltage range of 0.8–1.2 V, and a reliability of 96.1%–99.7% within a temperature range from <inline-formula> <tex-math>$- 10~{^{circ }}$ </tex-math></inline-formula>C to <inline-formula> <tex-math>$80~{^{circ }}$ </tex-math></inline-formula>C. Comparative analysis indicates that the proposed RMC PUF significantly outperforms existing structures in security, limiting the prediction accuracy of four ML attack models [logistic regression (LR), artificial neural networks (ANNs), deep neural networks (DNNs), and covariance matrix adaptive evolutionary strategy (CMA-ES)] to no more than 54.72%.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 8","pages":"2558-2570"},"PeriodicalIF":3.2,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148628153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"QSNNA: An Energy-Efficient Quaternary Spiking Neural Network Accelerator for Seizure Detection","authors":"Heng Zhang;Linfeng Wu;Linxiang Wang;Youbin Luo;Haochuan Pan;Xinyu Wang;Guoqiang He;Qinyu Chen;Yuxiang Fu;Li Li","doi":"10.1109/TVLSI.2026.3696357","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3696357","url":null,"abstract":"This work proposes a novel quaternary spiking neural network (QSNN) paradigm and its corresponding energy-efficient hardware accelerator to address the efficiency–accuracy tradeoffs in edge computing. Unlike traditional binary spiking neural networks (SNNs), the proposed architecture leverages multilevel spike magnitudes to enhance temporal representation density. To optimize hardware implementation, we introduce a low-complexity temporal feature fusion encoding (TFFE) scheme and an adaptive spike suppression mechanism (ASSM). Specifically, the TFFE scheme extracts time-domain features in time-series signal processing tasks to achieve efficient spike encoding, thereby circumventing complex encoding overheads. Furthermore, the ASSM dynamically exploits intrinsic neural sparsity to skip redundant computations, allowing for configurable trade-offs between inference latency and power consumption. Based on this algorithm–hardware codesign, the QSNN accelerator (QSNNA) is implemented in a 40-nm CMOS process. We validate the reliability and efficiency of this architecture through an epileptic seizure detection task using the CHB-MIT database. Experimental results demonstrate that the accelerator achieves a minimum energy consumption of <inline-formula> <tex-math>$0.066~mu $ </tex-math></inline-formula>J per inference and occupies a compact core area of 0.21 mm², representing a <inline-formula> <tex-math>$gt!3.4times $ </tex-math></inline-formula> reduction in energy compared to state-of-the-art (SOTA) accelerators. Simultaneously, the system attains high classification performance with accuracy <inline-formula> <tex-math>$geq 97.40$ </tex-math></inline-formula>%, sensitivity <inline-formula> <tex-math>$geq 96.74$ </tex-math></inline-formula>%, and specificity <inline-formula> <tex-math>$geq 97.88$ </tex-math></inline-formula>%, outperforming baseline methods.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 8","pages":"2369-2382"},"PeriodicalIF":3.2,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148626956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High-Performance FPGA-Based LZ77 Accelerator Design With Deep-Search Capability","authors":"Hao Xiao;Han Xu;Yu Ren;Saiqin Xu","doi":"10.1109/TVLSI.2026.3689072","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3689072","url":null,"abstract":"LZ77 is a fundamental primitive for lossless data compression in data-intensive systems. However, conventional hardware accelerators face a fundamental tradeoff between throughput and compression ratio (CR). To overcome this challenge, this brief presents a hardware accelerator tailored for deep-search-based LZ77 compression, achieving a high CR without sacrificing throughput. The proposed design introduces a multidimensional screening strategy built on a reconstructed hash table to aggressively prune invalid nodes and identify a compact set of high-quality candidates prior to high-latency string matching. By condensing the expanded search space induced by deep search, this approach significantly reduces matching complexity while preserving the compression benefits of deep exploration. Architecturally, we design a distributed hash table coupled with a cascaded matrix-simplification pipeline to alleviate memory contention and routing congestion arising from large-scale hash indexing. FPGA implementation achieves a throughput of 4.0 GB/s at 250 MHz and an average CR of 2.38 on the Calgary corpus.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 8","pages":"2631-2635"},"PeriodicalIF":3.2,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148628067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Energy-Efficient Block-Convolution-Based Super-Resolution Processor With Tiling Artifact Reduction","authors":"Byeungseok Yoo;Sungjin Park;Sunwoo Lee;Dongsuk Jeon","doi":"10.1109/TVLSI.2026.3690901","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3690901","url":null,"abstract":"Real-time super-resolution (SR) on edge devices preserves spatial resolution across all network layers, making memory traffic a dominant energy bottleneck. Block-convolution-based tile processing reduces memory access but introduces a tradeoff between the on-chip memory for boundary buffering and visible tiling artifacts. This article presents an energy-efficient SR processor that suppresses tiling artifacts with minimal on-chip data movement through algorithm–hardware codesign. We design a lightweight SR network that preserves boundary information only in the first layer and compensates for zero-padding errors via a boundary-preserving global offset path. Compared to full boundary buffering, this approach reduces the boundary memory footprint by 97.8% with a PSNR loss of less than 0.1 dB. The proposed SR processor integrates a unified multikernel core with a hybrid FP7-INT8 MAC unit optimized for the weight distribution and a reconfigurable grouped processing element (PE) array. Furthermore, intercore and intracore dataflow with layer fusion minimizes intermediate activation buffering and improves overall PE utilization under fused execution, reducing the total on-chip memory footprint by 80.5%. Implemented in a 28-nm FD-SOI process, the chip occupies 2.25 mm² with 30.4-kB on-chip SRAM and achieves 37.10-dB PSNR at <inline-formula> <tex-math>$595.7~mu $ </tex-math></inline-formula>J/frame for FHD (<inline-formula> <tex-math>$1920times 1080$ </tex-math></inline-formula>) resolution.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 8","pages":"2509-2522"},"PeriodicalIF":3.2,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148628279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Topology Optimization of 3-D NoC for High-Speed Data Acquisition Systems via Deep Reinforcement Learning","authors":"Yunhui Deng;Chuanpei Xu;Wei Mo;Chunting Wan","doi":"10.1109/TVLSI.2026.3690001","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3690001","url":null,"abstract":"The deployment of high-speed data acquisition systems (HS-DAQs) on 3-D network-on-chip (3-D NoC) requires the real-time transmission of large volumes of data across the network. However, conventional generic topology structures are difficult to adapt effectively to the specific communication characteristics of such systems, leading to degraded overall transmission efficiency. This article proposes a topology optimization methodology for 3-D NoC oriented toward HS-DAQ systems. The topology adjustment process is formulated as a sequential optimization task, and deep reinforcement learning is employed to progressively refine the network connections to better match the system communication load. A pruning–regrowth mechanism is introduced to reconstruct critical links, thereby achieving a balance between latency performance and area overhead. In addition, an action candidate set combined with a dual-level <inline-formula> <tex-math>$varepsilon $ </tex-math></inline-formula>-greedy strategy is adopted to enhance training stability and search efficiency in large-scale action spaces. Experimental results on HS-DAQ systems of different scales (16–48 nodes) demonstrate that, compared with the 3-D Mesh NoC and 3-D PC-NoC, the optimized network topology reduces the average latency by approximately 4.2%–14.3% and 11.7%–30.3%, the maximum path latency by about 13.6%–19.7%, and the edge area by 27.8%–33.3% and 5.6%–14.7%, respectively.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 7","pages":"2213-2226"},"PeriodicalIF":3.2,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148512809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"RAW-PM: Reliability-Aware Weighted Polar Mapping for Hard-Decision Decoding in 3-D NAND Flash Memory","authors":"Debao Wei;Huqi Xiang;Dixin Ma;Yongchao Wang;Liyan Qiao","doi":"10.1109/TVLSI.2026.3687257","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3687257","url":null,"abstract":"As 3-D <sc>nand</small> flash memory continues to scale toward higher density, significant reliability disparities arise among different pages in triple-level cell (TLC) flash, posing severe challenges to error-correction codes (ECCs) in the middle and late stages of flash lifetime. Polar codes have been introduced into flash storage systems due to their near-capacity performance; however, their decoding heavily relies on the accuracy of log-likelihood ratios (LLRs). Hard-decision sensing in flash memory leads to severe loss of soft information, thereby limiting the achievable error-correction performance. To address these challenges, this article proposes a page-aware reliability optimization scheme for polar codes in 3-D TLC flash memory. First, a page-aware polar bit mapping (PA-PBM) scheme is proposed, which exploits the mismatch between polar bit importance and page reliability by mapping critical bits to highly reliable pages and frozen bits to less reliable pages, thereby reducing the probability of critical errors. Building upon PA-PBM, a reliability-aware weighted polar mapping (RAW-PM) scheme is further developed, which incorporates page-level raw bit error rate (RBER) information to construct confidence-differentiated pseudo-soft LLRs and refines the bit mapping strategy, enabling weighted path metric (PM) correction and improving decoding accuracy under hard-decision sensing. Extensive experiments are conducted on a flash memory test platform to evaluate the proposed schemes. The results demonstrate that RAW-PM significantly improves the frame error-correction success rate in the middle and late stages of flash lifetime and reduces the post-ECC uncorrectable bit error rate (UBER) by more than one order of magnitude. Under typical large-scale access, RAW-PM introduces no additional read operations, requires no changes to the decoder architecture, and achieves these gains with minimal control and computational overhead, demonstrating excellent practical feasibility.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 7","pages":"2165-2175"},"PeriodicalIF":3.2,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148516683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}