一种用于心电检测的四阶可调带宽Gm-C滤波器，在0.5 V电源下实现−7.9 dBV IIP3

IF 3.1 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-06-11 DOI:10.1109/TVLSI.2025.3576360

Farzan Rezaei;Loai G. Salem

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引用次数: 0

摘要

本文介绍了一种用于ECG检测的四阶$G_{m}$ -C低通滤波器，尽管在0.5 V电源下工作，但通过1)将所采用的$G_{m}$级的差分对（DPs）置于双环反馈结构中，2)采用体驱动而不是门驱动的$G_{m}$ DPs，以及3)在传统的$G_{m}$级中使用电流镜代替级联编码晶体管，实现了高线性。在$0.18~\mu $ m CMOS样机上的测量结果表明，该滤波器在$V_{\text {DD}}$ 0.5 V的电压下工作，在高达340 mVpp的输入幅值下实现了低于- 40 dB的三阶谐波失真（HD3）。该滤波器在240hz带宽上的集成噪声为$154.7~\mu $ Vrms，动态范围（DR）为53.6 dB，与先前报道的作品相比具有竞争力。

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A Fourth-Order Tunable Bandwidth Gm-C Filter for ECG Detection Achieving −7.9 dBV IIP3 Under a 0.5 V Supply

This article introduces a fourth-order

$G_{m}$

-C low-pass filter for ECG detection that achieves high linearity despite operating under a 0.5 V supply by 1) placing the differential pairs (DPs) of the employed

$G_{m}$

stages in a two-loop feedback structure, 2) employing body-driven rather than gate-driven

$G_{m}$

DPs, and 3) using current mirrors in place of cascoded transistors in a conventional

$G_{m}$

stage. Measurement results of a

$0.18~\mu $

m CMOS prototype show that the proposed filter, operating with a

$V_{\text {DD}}$

of 0.5 V, achieves an third-order harmonic distortion (HD3) below −40 dB for input amplitudes up to 340 mV_pp. With an integrated noise of

$154.7~\mu $

V_rms over a 240-Hz bandwidth, the filter exhibits a dynamic range (DR) of 53.6 dB, which is competitive with previously reported works.

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.