Test Primitives: The Unified Notation for Characterizing March Test Sequences

IF 3.1 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-06-17 DOI:10.1109/TVLSI.2025.3577448

Ruiqi Zhu;Houjun Wang;Susong Yang;Weikun Xie;Yindong Xiao

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引用次数: 0

Abstract

March algorithms are essential for detecting functional memory faults, characterized by their linear complexity and adaptability to emerging technologies. However, the increasing complexity of fault types presents significant challenges to existing fault detection models regarding analytical efficiency and adaptability. This article introduces the test primitive (TP), a unified notation that characterizes March test sequences through a novel methodology that decouples fault detection operations from sensitization states. The proposed TP achieves platform independence and seamless integration of fault models, supported by rigorous theoretical proofs. These proofs establish the fundamental properties of the TP in terms of completeness, uniqueness, and conciseness, providing a theoretical foundation that ensures the decoupling method reduces the computational complexity of March algorithm analysis to

$O(1)$

. This reduction is analogous to Karnaugh map simplification in digital logic while enabling millisecond-level automated analysis. Experimental results demonstrate that the proposed method significantly enhances both analyzable fault coverage (FC) and detection accuracy, thereby addressing critical limitations of existing fault detection models.

查看原文本刊更多论文

测试原语：描述三月测试序列的统一符号

行军算法具有线性复杂性和对新兴技术的适应性，是检测功能性记忆故障的关键。然而，故障类型日益复杂，对现有故障检测模型的分析效率和适应性提出了重大挑战。本文介绍了测试原语（TP），这是一种统一的符号，通过一种新颖的方法来表征March测试序列，该方法将故障检测操作与敏化状态解耦。该方法实现了故障模型的平台无关性和无缝集成，并有严格的理论证明。这些证明建立了TP在完备性、唯一性和简洁性方面的基本性质，为确保解耦方法将March算法分析的计算复杂度降低到$O(1)$提供了理论基础。这种减少类似于数字逻辑中的卡诺地图简化，同时实现毫秒级的自动分析。实验结果表明，该方法显著提高了可分析故障覆盖率（FC）和检测精度，从而解决了现有故障检测模型的关键局限性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.