IDWA:一种基于低写验证比ram的内存计算的重要性驱动的权重分配算法

IF 3.1 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Jingyuan Qu;Debao Wei;Dejun Zhang;Yanlong Zeng;Zhelong Piao;Liyan Qiao
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引用次数: 0

摘要

基于电阻式随机存取存储器(RRAM)的内存计算(IMC)体系结构目前受到广泛关注。由于这种计算方法依赖于器件的模拟特性,因此RRAM的写入变化会在不同程度上影响计算精度。传统的写验证(W&V)过程对所有权重参数执行,导致大量的时间开销。为了解决这个问题,我们提出了一种训练算法,该算法可以以较低的W&V开销成本恢复受写入变化影响的离线IMC精度。在神经网络的训练过程中引入了一种重要性驱动的权重分配(IDWA)算法。该算法对不太重要的权值进行约束,抑制变异干扰在这部分权值上的扩散,从而减少不必要的精度下降。此外,我们采用分层优化算法来识别W&V操作中神经网络中的重要权重。在各种深度神经网络(dnn)架构和数据集上进行的广泛测试表明,我们提出的选择性W&V方法在准确性保持和计算效率方面始终优于当前最先进的选择性W&V技术。在相同的精度水平下,与其他先进方法相比,它提供了6倍的速度提升。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
IDWA: A Importance-Driven Weight Allocation Algorithm for Low Write–Verify Ratio RRAM-Based In-Memory Computing
Resistive random access memory (RRAM)-based in-memory computing (IMC) architectures are currently receiving widespread attention. Since this computing approach relies on the analog characteristics of the devices, the write variation of RRAM can affect the computational accuracy to varying degrees. Conventional write–verify (W&V) procedures are performed on all weight parameters, resulting in significant time overhead. To address this issue, we propose a training algorithm that can recover the offline IMC accuracy impacted by write variation with a lower cost of W&V overhead. We introduce a importance-driven weight allocation (IDWA) algorithm during the training process of the neural network. This algorithm constrains the values of less important weights to suppress the diffusion of variation interference on this part of the weights, thus reducing unnecessary accuracy degradation. Additionally, we employ a layer-wise optimization algorithm to identify important weights in the neural network for W&V operations. Extensive testing across various deep neural networks (DNNs) architectures and datasets demonstrates that our proposed selective W&V methodology consistently outperforms current state-of-the-art selective W&V techniques in both accuracy preservation and computational efficiency. At same accuracy levels, it delivers a speed improvement of $6\times \sim 32\times $ compared to other advanced methods.
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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