A Switched-Based Slew Rate and Gain Boosting Parallel-Path Amplifier for Switched-Capacitor Applications

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-04-22 DOI:10.1109/TVLSI.2025.3557467

Javad Bagheri Asli;Alireza Saberkari;Atila Alvandpour

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引用次数: 0

Abstract

A parallel-path amplifier (PPA) incorporating a switched-based slew rate and gain boosting stage as a feed-forward path, in parallel with a linear amplifier is introduced in this brief as an alternative to conventional analog amplifiers to achieve a high accuracy through the linear path and high slewing through the assisted feed-forward path. The feed-forward path employs a pre-amplifier, hysteresis-detector, and differential charge pumps, while the linear path includes a recycling folded-cascode amplifier. An analysis is performed to study the amplifier’s settling error with and without the feed-forward path, and also the trade-off between the dead-zone width of the hysteresis detector and the amplifier’s settling speed. The assisted feed-forward path has improved the slew rate

$\times 2.5$

–800 V/

$\mu $

s, effective GBW by 15%, and dc gain by 16 dB at the expense of adding

$187.5~\mu $

A extra current consumption and

$1.25~\mu $

m² extra silicon area. To prove the concept, the proposed amplifier is used as a multiplying digital-to-analog converter (MDAC) amplifier of an 8-bit pipeline analog-to-digital converter (ADC), and the ADC is fabricated in a 65-nm CMOS process. The results reveal that the spurious free dynamic range (SFDR) and signal-to-noise and distortion ratio (SNDR) performances are improved by 6–7 dB in the presence of the feed-forward path.

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一种用于开关电容的开关型摆率和增益提升并联路径放大器

本文简要介绍了一种并联路径放大器（PPA），该放大器采用基于开关的摆率和增益提升级作为前馈路径，与线性放大器并联，作为传统模拟放大器的替代方案，通过线性路径实现高精度，通过辅助前馈路径实现高回转。前馈路径采用前置放大器、迟滞检测器和差分电荷泵，而线性路径包括一个循环折叠级联放大器。分析了有前馈路径和无前馈路径时放大器的沉降误差，以及滞回检测器死区宽度与放大器沉降速度之间的权衡。辅助前馈电路提高了转换率2.5 ~ 800 V/ s，有效GBW提高了15%，直流增益提高了16 dB，但代价是增加了187.5~\mu $ A的额外电流消耗和1.25~\mu $ m2的额外硅面积。为了证明这一概念，所提出的放大器被用作8位流水线模数转换器（ADC）的乘法数模转换器（MDAC）放大器，并且该ADC采用65nm CMOS工艺制造。结果表明，采用前馈路径后，系统的无杂散动态范围（SFDR）、信噪比和失真比（SNDR）性能提高了6 ~ 7 dB。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.