基于ntt的串行和并行流水线多项式模乘法体系结构

IF 3.1 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Sin-Wei Chiu;Keshab K. Parhi
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引用次数: 0

摘要

量子计算机通过肖尔算法高效地解决整数分解等问题,对现代密码系统构成了重大威胁。基于带误差环学习(ring - lwe)的同态加密(HE)方案为加密数据的安全计算提供了一个抗量子框架。这些方案中的许多都依赖于多项式乘法,可以使用数论变换(NTT)在水平HE中有效地加速多项式乘法,从而确保隐私保护应用的实际性能。本文提出了一种新的基于ntt的串行流水线乘法器,该乘法器通过交错折叠实现了全硬件利用率,克服了传统串行R2MDC架构50%的利用率不足限制。此外,它还探讨了流水线并行设计中的权衡,包括串行、2并行和4并行架构。我们的设计利用了更高的并行性、高效的折叠技术,并对选定的恒定模量进行了优化,与最先进的实现相比,实现了更高的吞吐量(TP)。而串行折叠设计最大限度地减少面积消耗,4并行设计最大限度地提高TP。在Virtex-7平台上的实验结果表明,我们的架构在串行折叠设计中,当多项式长度为1024时,TP/面积至少提高2.22倍,当多项式长度为4096时,TP/面积至少提高1.84倍,而在4并行设计中,TP/面积分别至少提高2.78倍和2.79倍。效率增益在TP平方/面积上更加明显,其中,当多项式长度为1024时,串行折叠和4并行设计的性能分别优于先前的作品至少4.98倍和26.43倍,而当多项式长度为4096时,效率增益分别为6.7倍和43.77倍。这些结果突出了我们的架构在平衡性能、面积效率和灵活性方面的有效性,使它们非常适合高速加密应用。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Architectures for Serial and Parallel Pipelined NTT-Based Polynomial Modular Multiplication
Quantum computers pose a significant threat to modern cryptographic systems by efficiently solving problems such as integer factorization through Shor’s algorithm. Homomorphic encryption (HE) schemes based on ring learning with errors (Ring-LWE) offer a quantum-resistant framework for secure computations on encrypted data. Many of these schemes rely on polynomial multiplication, which can be efficiently accelerated using the number theoretic transform (NTT) in leveled HE, ensuring practical performance for privacy-preserving applications. This article presents a novel NTT-based serial pipelined multiplier that achieves full-hardware utilization through interleaved folding, and overcomes the 50% under-utilization limitation of the conventional serial R2MDC architecture. In addition, it explores tradeoffs in pipelined parallel designs, including serial, 2-parallel, and 4-parallel architectures. Our designs leverage increased parallelism, efficient folding techniques, and optimizations for a selected constant modulus to achieve superior throughput (TP) compared with state-of-the-art implementations. While the serial fold design minimizes area consumption, the 4-parallel design maximizes TP. Experimental results on the Virtex-7 platform demonstrate that our architectures achieve at least 2.22 times higher TP/area for a polynomial length of 1024 and 1.84 times for a polynomial length of 4096 in the serial fold design, while the 4-parallel design achieves at least 2.78 times and 2.79 times, respectively. The efficiency gain is even more pronounced in TP squared over area, where the serial fold and 4-parallel designs outperform prior works by at least 4.98 times and 26.43 times for a polynomial length of 1024 and 6.7 times and 43.77 times for a polynomial length of 4096, respectively. These results highlight the effectiveness of our architectures in balancing performance, area efficiency, and flexibility, making them well-suited for high-speed cryptographic applications.
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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