IEEE Transactions on Very Large Scale Integration (VLSI) Systems最新文献

{"title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information","authors":"","doi":"10.1109/TVLSI.2024.3517115","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3517115","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 1","pages":"C2-C2"},"PeriodicalIF":2.8,"publicationDate":"2024-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10818572","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Re-Pen: Reinforcement Learning-Enforced Penetration Testing for SoC Security Verification","authors":"Hasan Al Shaikh;Shuvagata Saha;Kimia Zamiri Azar;Farimah Farahmandi;Mark Tehranipoor;Fahim Rahman","doi":"10.1109/TVLSI.2024.3510682","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3510682","url":null,"abstract":"Due to the increasingly complex interaction between the tightly integrated components, reuse of various untrustworthy third-party IPs (3PIPs), and security-unaware design practices, there have been a rising number of reports of system-on-chip (SoC) hardware (HW) vulnerabilities that compromise the security of critical assets. SoC security verification, therefore, is an indispensable part of the verification effort. The existing hardware verification methodologies either presuppose white-box knowledge or scale poorly with increasing design complexity. Hardware penetration testing (pentest) is an emerging gray-box security verification methodology at the register-transfer level (RTL) that is applicable across a wide variety of threat models and addresses many shortcomings of the existing methodologies. In this work, we propose Re-Pen, a novel hardware pentest framework that requires minimal gray-box information from the design specification to achieve significantly better security vulnerability (SV) detection performance than state-of-the-art pentest techniques. At the core of this framework lies a mutation engine that combines the strengths of reinforcement learning (RL) and binary particle swarm optimization (BPSO) in its test pattern mutation strategy to generate intelligent test patterns without manual supervision. This framework significantly reduces the requirement for detailed, manual, expertise-driven adaptations specific to the SoC under test. Through extensive experiments conducted on multiple SoCs, we demonstrate that Re-Pen can reduce vulnerability detection time by up to <inline-formula> <tex-math>$3times $ </tex-math></inline-formula> and achieve a markedly improved consistency compared with the state of the art. Furthermore, Re-Pen was able to detect native security bugs in an open-source SoC. It successfully identified a scenario where, despite a functionally correct hardware implementation, a mistake in the architectural specification allowed privilege escalation from the software layer.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 3","pages":"853-866"},"PeriodicalIF":2.8,"publicationDate":"2024-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An MIV Fault Diagnosis Method Based on Signal Transmission Performance Analysis","authors":"Ziwen Xiao;Lifu Du;Zhiming Yang;Cuiyu Liu;Yang Yu","doi":"10.1109/TVLSI.2024.3518554","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3518554","url":null,"abstract":"Monolithic inter-tier vias (MIVs) in monolithic 3-D integrated circuits (M3D ICs) enables massive vertical integration. However, MIVs are more susceptible to defects due to high integration density and complex manufacturing processes. Existing MIV test techniques can effectively detect and locate MIV faults, but diagnosable fault types are limited. We propose a novel fault diagnosis method based on signal transmission performance analysis. This method can diagnose more fault types, including resistive open, hard open, short, and leakage faults. In the proposed solution, fault diagnosis can be carried out by comprehensively monitoring voltage and delay characteristics of MIVs. The effectiveness of fault diagnosis is verified through high speed simulation program with integrated circuit emphasis (HSPICE) simulations. We also perform Monte Carlo simulations to prove that the proposed method has high robustness even in the case of process variations. Experimental results show that the proposed method has low hardware overhead while ensuring high diagnostic resolution.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 4","pages":"1145-1156"},"PeriodicalIF":2.8,"publicationDate":"2024-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143676063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Built-In Self-Repair of Small Delay Faults Occurring to TSVs in a 3D-DRAM Using an Enhanced Pulse-Vanishing Test","authors":"Chen-Yu Huang;Shi-Yu Huang","doi":"10.1109/TVLSI.2024.3514732","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3514732","url":null,"abstract":"In a 3D-DRAM, multiple DRAM dice are stacked together and bonded vertically with through-silicon vias (TSVs). It is known that a 3D-DRAM could operate at a very high speed, and even a small delay fault could cause a failure. Even though numerous prior works have been proposed to perform built-in self-repair (BISR) for faulty TSVs in a 3D-DRAM, they cannot handle sub-100-ps small delay faults easily. In this work, we aim to fix this problem with a “progressively shrinking pulse-vanishing test (PV-Test).” Our BISR scheme streamlines the entire test-and-repair (TAR) process integrating several techniques, including small-delay-fault detection, on-the-spot diagnosis, test result broadcasting, TSV repair, and the final validation. The experimental results show that it can indeed detect and repair a small delay fault that causes a sub-100-ps extra delay on a TSV.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 4","pages":"1132-1144"},"PeriodicalIF":2.8,"publicationDate":"2024-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143675674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High-Reliability and High-Throughput CIM 10T-SRAM for Multiplication and Accumulation Operations With 274.3 GOPS and 200–237.5 TOPS/W","authors":"Wenjuan Lu;Lubin Xiang;Ling Wang;Chunyu Peng;Chenghu Dai;Zhiting Lin;Xiulong Wu","doi":"10.1109/TVLSI.2024.3519748","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3519748","url":null,"abstract":"Artificial intelligence (AI) is extensively applied in natural language processing, image matching, and image recognition, with convolutional neural networks (CNNs) being crucial. Computing-in-memory (CIM) utilizing static random access memory (SRAM) can enhance the CNN performance. However, this faces issues such as multibit signed data processing, read corruption of traditional SRAM arrays, and increased area overhead due to increased capacitor weighting. This article proposes a 10T-SRAM macro tailored for CNN multiply-accumulate calculation (MAC) computation in image processing. It enables high-throughput full-array operations, with added dual ports facilitating input of multibit data with signed bits. The 10T-SRAM cell features a read-write separation channel, mitigating read disturbance issues seen in dual-port 8T-SRAM arrays or 6T-SRAM arrays. Incorporating redundant columns in the array for charge sharing and weighting conserves area and boosts circuit reliability. In the 28-nm CMOS simulation environment, the proposed architecture achieves a throughput of 274.3 GOPS and an energy efficiency of 200–237.5 TOPS/W, surpassing literature-reported figures by several times.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 4","pages":"1073-1081"},"PeriodicalIF":2.8,"publicationDate":"2024-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143675670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"ATEP: An Asynchronous Timing Error Prediction Circuit With Adaptive Voltage and Frequency Scaling","authors":"Chenghong Zhang;Dongliang Xiong;Xiaoxu Zhang;Zhengyu Wang;Huibo Gao;Kai Huang","doi":"10.1109/TVLSI.2024.3510697","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3510697","url":null,"abstract":"Timing error prediction circuits have demonstrated greater efficiency in reducing the worst case timing margins of conventional circuits. However, prior works of timing error prediction circuits have complicated the clock tree or introduced a substantial number of delay cells along data paths, resulting in a considerable increase in area overhead. This work introduces asynchronous timing error prediction circuit (ATEP), an ATEP that integrates timing error prediction technology with bundle-data asynchronous templates. The proposed circuit leverages delay lines in the request wire to generate the warning detection window (WDW) independent of clock signals, thereby reducing area overhead and streamlining the clock tree. In addition, we present an adaptive voltage and frequency scaling (AVFS) controller, which evaluates the likelihood of warnings or the quantity of warning paths based on path activation rates to determine when to cease adjustments. This strategy helps to identify the frequency closer to the point of first failure (PoFF). Furthermore, we propose a dynamic warning detector gating strategy to gate warning detectors based on the current environment, further decreasing power consumption. Implementing this circuit on an RISC-V processor, targeting 28-nm CMOS technology, yields up to a 56.8% performance improvement with only a 3.79% area cost and up to a 28.0% reduction in power consumption.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 5","pages":"1396-1406"},"PeriodicalIF":2.8,"publicationDate":"2024-12-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143875163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Single-Ended/Differential Wideband Track-and-Hold Amplifier in 22-nm FD-SOI CMOS Process","authors":"Zixian Zheng;Wei Shu;Joseph S. Chang","doi":"10.1109/TVLSI.2024.3518512","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3518512","url":null,"abstract":"The impending 6G communication based on the software defined radio (SDR) requires a radio frequency (RF) track-and-hold amplifier (THA). This THA serves as the frequency down-converter and the single-to-differential interface to the downstream analog-to-digital converter (ADC). We present a CMOS RF THA that features wide and width (18 GHz), yet high linearity (spurious free dynamic range (SFDR) of 56.7 dB) and not requiring an external balun. These features are derived from our proposed isolation technique based on our proposed double source follower enhanced (DSFE) structure. To realize the single-to-differential conversion without an external balun, we design an independent balun as the first stage. Thereafter, we employ our proposed feedforward compensation technique (FCT) along with the reported phase correction technique (PCT) to reduce the output mismatches while simultaneously enhancing the linearity and bandwidth. We monolithically realize the RF THA in 22-nm fully-depleted silicon-on-insulator (FD-SOI) CMOS operating at 1.8 V. Measurements depict that the input bandwidth is wide (18 GHz), yet featuring high linearity (SFDR =56.7 dB at 15 GHz) with 2 GS/s sampling rate. The power consumption and the chip area are low and small at 216 mW and 0.07 mm2, respectively. When benchmarked against reported III/V RF THAs, the proposed CMOS RF THA is very competitive—comparable bandwidth, yet simultaneously higher linearity, potentially lower cost, lower power dissipation, and smaller die area. Further because it is realized in CMOS, it facilitates integration to other CMOS circuits in the same system-on-chip (SoC).","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 4","pages":"942-952"},"PeriodicalIF":2.8,"publicationDate":"2024-12-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143676062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"On Using nMOS-pMOS-Type Cells in a Threshold-Voltage Compensated CMOS RF-DC Rectifier","authors":"Yoomi Park;Sangjin Byun","doi":"10.1109/TVLSI.2024.3515110","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3515110","url":null,"abstract":"In this brief, we discuss the merits of using nMOS-pMOS (NP)-type cells instead of nMOS-nMOS (NN)- or pMOS-pMOS (PP)-type cells in a single-ended, threshold-voltage compensated CMOS RF-dc rectifier. By adopting the NP-type cells, we can avoid the degradation of the generated output dc voltage due to parasitic long interconnection wire capacitance, deep N-well to P-substrate junction capacitance, and additional body effect. For comparison, we have implemented two RF-dc rectifiers in a 28-nm 1P11M CMOS process. The measured results show that the implemented RF-dc rectifier with the NP-type cells achieves 0.7-dB higher input power sensitivity and <inline-formula> <tex-math>$3times $ </tex-math></inline-formula> faster recharging time than the other rectifier with the NN-type cells.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 5","pages":"1472-1476"},"PeriodicalIF":2.8,"publicationDate":"2024-12-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143875164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High Signal-to-Noise Ratio and High-Sensitivity 4-D LiDAR Imaging Receiver","authors":"Jianping Guo;Zhengping Gao;Xiaoyang Zeng;Wenhong Li;Mingyu Wang","doi":"10.1109/TVLSI.2024.3498867","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3498867","url":null,"abstract":"This brief designs and implements a 4-D imaging light detection and ranging (LiDAR) receiver. It employs a reconfigurable transimpedance amplifier (TIA) that alternates between two modes to separately achieve ranging and light intensity quantification functions. A new mode-switching method based on a monostable multivibrator is proposed, allowing the TIA to automatically switch modes during measurement. The reconfigurable TIA and mode-switching method enable the application of charge sampling in 4-D LiDAR imaging receiver, resulting in a higher signal-to-noise ratio (SNR) compared with traditional designs. In addition, the TIA mode used for distance measurement achieves a bandwidth of 140 MHz, a gain of <inline-formula> <tex-math>$99.8~text {dB}Omega $ </tex-math></inline-formula>, and an input-referred noise of ~20-nA rms, indicating high detection sensitivity. A prototype implemented in 0.18-um CMOS verifies the feasibility of the proposed receiver, consuming 24.5 mW. Measurement results demonstrate that the prototype can effectively acquire distance and light intensity information of target objects within a range of 5 m.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 5","pages":"1437-1441"},"PeriodicalIF":2.8,"publicationDate":"2024-12-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143875071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Efficient Pipelined Hardware Architecture for Depth-Map-Based Image Dehazing System","authors":"K. Vidyamol;M. Surya Prakash;Praveen Sankaran","doi":"10.1109/TVLSI.2024.3519262","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3519262","url":null,"abstract":"Hazy images can be made clear with the image dehazing process. Advanced driver-assistance systems (ADASs) may have a preexisting stage to maintain clear driving visuals in foggy situations. ADAS strives for greater image resolution at a faster frame rate in order to maintain its dependability for road safety. This tendency forces image dehazing to contend with a formidable throughput challenge with improved power constraints. This work proposes a hardware-efficient, computationally light image dehazing engine. It consists of two main techniques: the saturation-based local airlight estimation module (SLAEM) and the depth-map transmission-map estimation unit (DMTMEU). The transmission-map estimation task and the airlight estimate task can be executed concurrently due to the adopted depth map-based transmission estimation approach, eliminating the dependence between the two activities. In terms of pixels, an additional advantage of the adaptive airlight estimation approach is that it avoids the computationally demanding sorting step, which helps to increase hardware efficiency. The entire architecture utilizes look-up table (LUT)-based computations to implement division modules and exponential functions, resulting in more optimized architecture than the existing dehazing architectures. The Taiwan Semiconductor Manufacturing Company (TSMC) CMOS 90-nm technology is used in the implementation of this study. It is arranged into a six-stage pipelining approach to create a seamless data scheduling process. It achieves a throughput of 200 Mp/s with a logic gate count of 9.309 K and a power consumption of 2.61 mW at 200 MHz. The experimental results demonstrate a 20.09% reduction in area and a 31.31% reduction in power compared to best-performed existing systems, highlighting significant performance improvement.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 4","pages":"1082-1093"},"PeriodicalIF":2.8,"publicationDate":"2024-12-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143675671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}