IEEE Transactions on Very Large Scale Integration (VLSI) Systems最新文献_第6页

Design of High-Speed Multimodulus Divider With Fast EOC Generation Counters and High-Speed Reset Configuration 具有快速EOC生成计数器和高速复位配置的高速多模分频器设计

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-07-01 Epub Date: 2026-04-27 DOI: 10.1109/TVLSI.2026.3684891

Yunrui Zhao;Pei Qin;Quan Xue

{"title":"Design of High-Speed Multimodulus Divider With Fast EOC Generation Counters and High-Speed Reset Configuration","authors":"Yunrui Zhao;Pei Qin;Quan Xue","doi":"10.1109/TVLSI.2026.3684891","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3684891","url":null,"abstract":"A high-speed multimodulus divider (MMD) is proposed in a 65-nm CMOS process. A 7-bit programmable counter (PC) featuring an innovative end-of-count (EOC) architecture and high-speed reset configuration is proposed for MMD applications. The proposed PC achieves an operating frequency of 11.7 GHz, which is 64.8% higher than the previously reported state-of-the-art design. In addition, an innovative analogous digital-standard-cell (A-STD) layout methodology is introduced to optimize parasitic capacitance and chip area in MMD implementation. By utilizing the above techniques along with a 20.5 GHz high-speed true-single-phase-clock (TSPC) dual-modulus prescaler (DMP), the MMD achieves a division-ratio range from 40 to 323, with a maximum frequency of 12.6 GHz at 1.2-V supply, consuming a total power of 3.07 mW. And by using the A-STD layout methodology, the MMD occupies a small chip area. The chip area of MMD is <inline-formula> <tex-math>$56 times 36 {,}boldsymbol {mu }text {m}^{2}$ </tex-math></inline-formula>, which is less than 20% of that of prior works with similar functionality.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 7","pages":"2126-2138"},"PeriodicalIF":3.2,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148514575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A High-Precision Reference-Free Relaxation Oscillator With Supply-Tracking Switching Threshold 具有供电跟踪开关阈值的高精度无参考弛豫振荡器

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-07-01 Epub Date: 2026-04-14 DOI: 10.1109/TVLSI.2026.3682877

Chuanhang Shao;Min Song;Zhen Zhang;Jichao Sui;Ming Zhang;Yin Zhang;Zhangqing He;Meilin Wan

{"title":"A High-Precision Reference-Free Relaxation Oscillator With Supply-Tracking Switching Threshold","authors":"Chuanhang Shao;Min Song;Zhen Zhang;Jichao Sui;Ming Zhang;Yin Zhang;Zhangqing He;Meilin Wan","doi":"10.1109/TVLSI.2026.3682877","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3682877","url":null,"abstract":"Conventional relaxation oscillators typically rely on reference circuits to generate switching threshold voltages or charging currents, resulting in increased chip area and power consumption. This article presents a high-precision relaxation oscillator that eliminates the need for reference circuits. A holding capacitor is charged through a timing resistor, and the switching threshold voltage is directly derived from the power supply using a resistor divider. Since both the charging speed and the switching threshold voltage scale with <inline-formula> <tex-math>$V_{!D!D}$ </tex-math></inline-formula>, their dependencies cancel each other out, resulting in an oscillation period determined solely by the time constant of the holding capacitor and timing resistor. Moreover, the tracking behavior of the switching threshold with respect to <inline-formula> <tex-math>$V_{!D!D}$ </tex-math></inline-formula> further reduces the sensitivity of the comparator delay to supply voltage variations. A dual-path charge–discharge scheme is also employed to eliminate frequency deviations caused by digital logic delays and capacitor discharge time. Fabricated in a 110-nm CMOS process, the oscillator operates at 24.5 MHz with an active area of 0.026 mm2. Measurement results indicate a power consumption of <inline-formula> <tex-math>$160~mu $ </tex-math></inline-formula>W and a maximum frequency error of 1.88% across a temperature range from −55 °C to 125 °C, corresponding to a temperature coefficient of 140 ppm/°C. When <inline-formula> <tex-math>$V_{!D!D}$ </tex-math></inline-formula> increases from 3.0 to 3.6 V, the output frequency variation is 0.4%.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 7","pages":"2074-2085"},"PeriodicalIF":3.2,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148515464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 55 MHz Bandwidth and Sub-μV Offset Precision Amplifier With Two-Step Dynamic Offset Calibration and Noise Suppression Techniques 一种55 MHz带宽和亚μ v偏置精度放大器，采用两步动态偏置校准和噪声抑制技术

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-07-01 Epub Date: 2026-03-04 DOI: 10.1109/TVLSI.2026.3668196

Yang Zhang;Xinyan Xue;Zi Wang;Mingyi Chen

{"title":"A 55 MHz Bandwidth and Sub-μV Offset Precision Amplifier With Two-Step Dynamic Offset Calibration and Noise Suppression Techniques","authors":"Yang Zhang;Xinyan Xue;Zi Wang;Mingyi Chen","doi":"10.1109/TVLSI.2026.3668196","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3668196","url":null,"abstract":"A fully differential offset-stabilized amplifier with a two-step dynamic offset calibration achieving sub-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>V offset and a 55 MHz gain-bandwidth product (GBW) is presented. The two-step offset calibration combines digitally-assisted auto-calibration with dynamic offset compensation (DOC) that maintains ultralow residual offset. The slow-settling auto-zeroing (AZ) technique is integrated with a proposed chopping scheme, which suppresses noise across the entire bandwidth, enabling higher bandwidth operation with reduced ripple and noise aliasing. Fabricated in a 180 nm BCD process, the prototype occupies an area of 1.32 mm2. The measurements show that the input-referred offset standard deviation is reduced by 99.97%, from 0.8 mV to 206 nV. Furthermore, the noise spectrum is nearly flat with the high-frequency ripple effectively suppressed. A noise floor of 7.8 nV/<inline-formula> <tex-math>$boldsymbol {surd }$ </tex-math></inline-formula>Hz has been achieved, corresponding to a noise efficiency factor (NEF) of 15. These results demonstrate its potential to be widely adopted in high-accuracy and high-bandwidth applications.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 7","pages":"2033-2040"},"PeriodicalIF":3.2,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148515845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Low-Latency Hardware Architecture Design for Five-Error-Correcting Reed--Solomon Decoder 五纠错Reed- Solomon译码器的低延迟硬件架构设计

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-07-01 Epub Date: 2026-03-11 DOI: 10.1109/TVLSI.2026.3689157

Haobin Xu;Zichuan Qiu;Suwen Song;Zhongfeng Wang;Liyang Zhou

{"title":"A Low-Latency Hardware Architecture Design for Five-Error-Correcting Reed--Solomon Decoder","authors":"Haobin Xu;Zichuan Qiu;Suwen Song;Zhongfeng Wang;Liyang Zhou","doi":"10.1109/TVLSI.2026.3689157","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3689157","url":null,"abstract":"Reed–Solomon (RS) codes are widely used in modern communication and storage systems. However, conventional iteration-based RS decoder architectures are struggling to meet the stringent demands of emerging latency-critical applications. Although noniterative architectures have been proposed for <inline-formula> <tex-math>$t leq 4$ </tex-math></inline-formula> RS codes with low latency and low complexity, the design of such architectures remains largely unexplored for five-error-correcting RS codes. Motivated by this gap, we extend the Peterson–Gorenstein–Zierler (PGZ) algorithm to directly compute the error locator polynomial for <inline-formula> <tex-math>$t=5$ </tex-math></inline-formula> RS codes, thereby eliminating the need for iterative computation in the circuit. Then, a systematic three-step optimization method is further proposed to mitigate the hardware complexity increase caused by PGZ, which significantly decreases the required number of multipliers. Besides, given the prohibitive complexity of noniterative root-finding algorithms for <inline-formula> <tex-math>$t = 5$ </tex-math></inline-formula> RS codes, we instead adopt a hybrid PGZ-Chien search (PGZ-CS) architecture for the whole decoder. Based on the proposed methods, a low-latency and area-efficient <inline-formula> <tex-math>$t=5$ </tex-math></inline-formula> RS decoder is finally developed and implemented under the example RS(255, 245, and 5) code. Synthesized under 28-nm CMOS technology, the proposed decoder reduces decoding latency by 65.6%, overall area by 29.7%, and power consumption by 32.6% compared to the compensated simplified reformulated inversionless Berlekamp–Massey (CS-RiBM) decoder.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 7","pages":"2321-2325"},"PeriodicalIF":3.2,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148442538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Real-Time End-to-End Event-Based Tactile Sensing System 实时端到端基于事件的触觉传感系统

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-07-01 Epub Date: 2026-02-18 DOI: 10.1109/TVLSI.2026.3663124

Yuncheng Lu;Kiho Seong;Si En Ng;Shibi Varku;Arindam Basu;Nripan Mathews;Tony Tae-Hyoung Kim

{"title":"A Real-Time End-to-End Event-Based Tactile Sensing System","authors":"Yuncheng Lu;Kiho Seong;Si En Ng;Shibi Varku;Arindam Basu;Nripan Mathews;Tony Tae-Hyoung Kim","doi":"10.1109/TVLSI.2026.3663124","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3663124","url":null,"abstract":"Event-based tactile sensing offers a promising alternative to frame-based approaches by reducing data redundancy, yet existing systems often lack end-to-end hardware support and remain power-inefficient. This work presents an energy-efficient event-based tactile sensing system that codesigns algorithms and hardware for real-time perception. At the front end, a leakage-compensated event-driven readout circuit integrates multiple tactile sensors into a single node, minimizing wiring and static power. At the algorithm level, a 2-D convolutional neural network (CNN) reconstructs event frames for handwritten digit recognition with strong robustness to varying interaction durations, while a graph neural network (GNN) processes irregular tactile layouts for object classification. A customized event-based tactile processor (ETP) supports end-to-end tactile processing, incorporating a dual-mode event frame builder (EFB) and a neural network processing unit (NPU) with an optimized data-reuse scheme. Evaluated using 28-nm CMOS, the ASIC performs handwritten digit recognition and object classification in 0.44 and 0.37 ms, respectively. The system consumes the total power of 5.2 mW with only 0.11-mW dynamic power, demonstrating an efficient solution for always-on tactile perception.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 7","pages":"2041-2053"},"PeriodicalIF":3.2,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148513020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Prototyping JSCC on FPGA: A Swin Transformer Accelerator Toward High-Effciency Semantic Communications 基于FPGA的JSCC原型设计：实现高效语义通信的Swin变压器加速器

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-07-01 Epub Date: 2026-04-29 DOI: 10.1109/TVLSI.2026.3683054

Xiaojun Zhang;Yue Liu;Xin Song;Jian Gao;Yanfei Dong;Xianqing Huang;Kai Niu;Jincheng Dai

{"title":"Prototyping JSCC on FPGA: A Swin Transformer Accelerator Toward High-Effciency Semantic Communications","authors":"Xiaojun Zhang;Yue Liu;Xin Song;Jian Gao;Yanfei Dong;Xianqing Huang;Kai Niu;Jincheng Dai","doi":"10.1109/TVLSI.2026.3683054","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3683054","url":null,"abstract":"Deep joint source-channel coding (deep JSCC) has emerged as a pivotal technology in the field of semantic communication. However, the complex structure of Swin Transformer results in low throughput and high power consumption, which poses challenges for deployment. To address this issue, we propose a field-programmable gate array (FPGA)-based Swin Transformer decoding accelerator. In this accelerator, a configurable matrix multiplication unit (CMMU) is designed. By adopting an input-stationary data flow combined with the NHWC storage format, it can dynamically reconfigure to accommodate both fully connected and convolutional neuron operations. An adaptive window strategy is presented to enable the computation unit to be compatible with the operations of fixed windows and shifted windows in the multihead self-attention (MHSA) mechanism. Furthermore, we propose a layerwise mixed-precision quantization scheme to lower the computational overhead. The accelerator is implemented on the Altera Stratix 10 platform. Operating at 200 MHz, it achieves a throughput of 400.36 GOPS, which is <inline-formula> <tex-math>$34.1 times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$3.6 times $ </tex-math></inline-formula> higher than the CPU and GPU implementations, respectively, while delivering superior energy efficiency. In addition, the accelerator attains 0.252 GOPS/DSP and 29.09 GOPS/W, comparing favorably against other related FPGA-based solutions in both resource and power efficiency.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 7","pages":"2227-2237"},"PeriodicalIF":3.2,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148513079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of an Approximate Recursive Multiplier Based on Probability-Driven Intercolumn Error Cancellation and Its Application in Deep Neural Networks 基于概率驱动列间误差抵消的近似递归乘法器设计及其在深度神经网络中的应用

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-07-01 Epub Date: 2026-04-27 DOI: 10.1109/TVLSI.2026.3686238

Shuo Cai;Wen He;Huilei Huang;Zhengbang Long

{"title":"Design of an Approximate Recursive Multiplier Based on Probability-Driven Intercolumn Error Cancellation and Its Application in Deep Neural Networks","authors":"Shuo Cai;Wen He;Huilei Huang;Zhengbang Long","doi":"10.1109/TVLSI.2026.3686238","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3686238","url":null,"abstract":"This article proposes a probability-driven intercolumn error cancellation mechanism for approximate multiplier design, enabling an improved tradeoff between computational accuracy and hardware efficiency. By statistically characterizing the error behavior of approximate compressors and coordinating positive and negative error units, effective column-level error cancellation is achieved. A subarray truncation strategy is further integrated into a recursive multiplier architecture to reduce partial product generation and accumulation overhead. Multiple approximate multipliers with different accuracy levels are implemented and synthesized in a 28-nm CMOS process. Compared with an exact <inline-formula> <tex-math>$8{,}times{,} 8$ </tex-math></inline-formula> multiplier, the high-accuracy ECM8-1 achieves near-lossless accuracy while reducing the power–area–delay product (PADP) by 35.6%, whereas the low-power ECM-TT22 achieves a reduction of up to 99.6%. In image processing applications, the high-accuracy and low-power designs achieve 99.8% and above 85.4% Structural Similarity Index (SSIM) in blurring, and 99.6% and 84.9% SSIM in edge detection, respectively. In quantized deep neural networks (DNNs) inference workloads, ECM8 incurs less than 0.3% accuracy loss on CIFAR-10, while ECM-O and ECM-T maintain near-exact performance on MNIST, demonstrating robustness across different precision levels and suitability for hardware-efficient DNN acceleration.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 7","pages":"2139-2150"},"PeriodicalIF":3.2,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148515603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Structured-Sparsity-Based Design Approach for Energy-Efficient Spiking Transformer Processing 一种基于结构稀疏性的节能尖峰变压器处理设计方法

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-07-01 Epub Date: 2026-03-25 DOI: 10.1109/TVLSI.2026.3675299

Hyunseok Jung;Kyungchul Lee;Jongsun Park

{"title":"A Structured-Sparsity-Based Design Approach for Energy-Efficient Spiking Transformer Processing","authors":"Hyunseok Jung;Kyungchul Lee;Jongsun Park","doi":"10.1109/TVLSI.2026.3675299","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3675299","url":null,"abstract":"Spiking transformers (STs) have emerged as promising architectures that achieve competitive accuracy with artificial neural network (ANN) on large-scale datasets. Despite this progress, the efforts to reduce the computational complexity of spiking self-attention (SSA) have seldom been explored. In this work, we present sparsity-based design approaches to reduce the computational complexity of SSA execution by systematically exploiting the structured sparsity in SSA. The proposed approaches are based on the observation that SSA naturally exhibits structured sparsity, which can be exploited to identify and skip redundant computations in SSA blocks. First, by employing a novel fully spiking SSA operator (FSSA) incorporating additional leaky integrate-and-fire (LIF) neurons, the average structured sparsity of SSA has been increased by <inline-formula> <tex-math>$1.8times $ </tex-math></inline-formula> with less than 1% loss in accuracy. In addition, by adopting a filtering strategy that ignores neurons with low spike rate when detecting structured sparsity, additional <inline-formula> <tex-math>$1.5times $ </tex-math></inline-formula> structured sparsity has been achieved compared to FSSA with negligible accuracy loss. Then, a sparsity-aware dataflow and hardware design convert the proposed structured sparsity patterns into runtime skipping of computations and weight transfers in SSA block execution. In postsynthesis simulations across the evaluated models, the proposed SSA operator with filtering techniques improve SSA block effective throughput and energy efficiency to 234.44 GOP/s and 319.12 GOP/J while keeping model accuracy loss below 1%, corresponding to 24.3% and 28.2% gains over the baseline spiking neural network (SNN) accelerator.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 7","pages":"2064-2073"},"PeriodicalIF":3.2,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148516123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Guest Editorial: Special Section on the Asia Pacific Conference on Circuits and Systems—APCCAS 2025 嘉宾评论：亚太电路与系统会议- apccas 2025特别部分

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-07-01 Epub Date: 2026-06-30 DOI: 10.1109/TVLSI.2026.3693816

Youngmin Kim;Junghwan Han;Won-Young Lee;Hui Wang

引用次数: 0

A Fully Synthesizable 12-bit Event-Driven TDC-Assisted Two-Step Counter for Imagers Achieving 0.49-LSB INL in 28-nm CMOS 一种完全可合成的12位事件驱动tdc辅助两步计数器，用于在28纳米CMOS中实现0.49 lsb INL

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-07-01 Epub Date: 2026-03-01 DOI: 10.1109/TVLSI.2026.3687014

Jinha Kim;Seyeon Kim;Jaehoon Jun

{"title":"A Fully Synthesizable 12-bit Event-Driven TDC-Assisted Two-Step Counter for Imagers Achieving 0.49-LSB INL in 28-nm CMOS","authors":"Jinha Kim;Seyeon Kim;Jaehoon Jun","doi":"10.1109/TVLSI.2026.3687014","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3687014","url":null,"abstract":"This brief presents a fully synthesizable 12-bit event-driven time-to-digital converter (TDC)-assisted two-step counter for column-parallel single-slope analog-to-digital converters (SS-ADCs) in image sensors. The proposed two-step architecture employs a 10-bit hybrid coarse counter—comprising a 2-bit Gray counter and an 8-bit ripple counter—with a 2-bit event-driven TDC for fine counting. A dual-edge stop generator triggers the event-driven TDC only on a comparator output (<italic>CMP<inline-formula> <tex-math>${}_{mathrm {OUT}}$ </tex-math></inline-formula>) transition, so the event-driven TDC is active for no longer than half a counter clock (<italic>CLK<inline-formula> <tex-math>${}_{mathrm {CNT}}$ </tex-math></inline-formula>) period, effectively reducing dynamic power consumption. Since coarse and fine operations proceed in parallel, the required conversion time for 12-bit quantization is reduced to one quarter of that of a ripple-counter-only approach. With an active area of <inline-formula> <tex-math>$62.04~mu $ </tex-math></inline-formula>m2, the prototype was fabricated in a 28-nm CMOS process using only standard cells. The measured power consumption is <inline-formula> <tex-math>$1.48~mu $ </tex-math></inline-formula>W, achieving 72.1% and 53.3% power reduction compared with the conventional 12-bit two-step and ripple-counter-based implementations, respectively. The event-driven TDC for residual time quantization consumes only 34 nW. The measured integral nonlinearity (INL) is +0.49/–0.47 LSB with an operating clock of 1.16 GHz, confirming relatively high linearity for imagers.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 7","pages":"2316-2320"},"PeriodicalIF":3.2,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148442675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0