IEEE Transactions on Very Large Scale Integration (VLSI) Systems最新文献_第7页

ZACHO: Zero-Shot Agile Circuit Hardening Optimizer via Deep Reinforcement Learning 基于深度强化学习的零射击敏捷电路强化优化器

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-07-01 Epub Date: 2026-04-14 DOI: 10.1109/TVLSI.2026.3681140

Junfeng Zhu;Yueming Hu;Liang Wang;Zhe Li;Yan Li;Xiaoyang Zeng

{"title":"ZACHO: Zero-Shot Agile Circuit Hardening Optimizer via Deep Reinforcement Learning","authors":"Junfeng Zhu;Yueming Hu;Liang Wang;Zhe Li;Yan Li;Xiaoyang Zeng","doi":"10.1109/TVLSI.2026.3681140","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3681140","url":null,"abstract":"As integrated circuits (ICs) continue to scale, soft errors pose a growing threat to system reliability—particularly in safety-critical applications. Among various circuit components, flip-flops (FFs) are especially susceptible to soft errors due to their state-holding nature, making them prime targets for selective hardening. However, such hardening introduces area and power overheads, necessitating careful tradeoffs. Existing methods typically rely on multiobjective optimization (MOO) algorithms to identify Pareto-optimal hardening strategies, yet their inherent randomness limits controllability, and they must be rerun entirely for each new circuit instance, resulting in poor adaptability. In this work, we propose a deep reinforcement learning (DRL)-based hardening optimizer that supports zero-shot generalization to unseen circuits. Built upon the advantage actor–critic (A2C) framework, our model is trained on synthetic circuits and learns to make sequential hardening decisions under strict resource constraints. A recurrent neural network (RNN) captures the historical context of prior hardening steps, while an attention mechanism dynamically focuses on FFs with high soft-error vulnerability at each decision step. Experimental evaluations on benchmark circuits demonstrate that our proposed framework achieves an average hypervolume (HV) improvement of 19.58%. Furthermore, the framework provides at least a <inline-formula> <tex-math>$9.9times $ </tex-math></inline-formula> runtime speedup for individual circuits, offering an agile and generalizable solution for reliability-centric circuit design. The source code is available at <uri>https://github.com/Magic00JuJu/ZACHO/tree/main</uri>","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 7","pages":"2260-2273"},"PeriodicalIF":3.2,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148514851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Algorithm--Hardware Co-Design of Digital Compute-in-Memory Architecture Supporting Flexible and Temporal N:M Sparsity 支持灵活和时间N:M稀疏性的数字内存计算体系结构的算法-硬件协同设计

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-07-01 Epub Date: 2026-03-05 DOI: 10.1109/TVLSI.2026.3686720

Akshat Ramachandran;Souvik Kundu;Arnab Raha;Shamik Kundu;Deepak A. Mathaikutty;Tushar Krishna

{"title":"Algorithm--Hardware Co-Design of Digital Compute-in-Memory Architecture Supporting Flexible and Temporal N:M Sparsity","authors":"Akshat Ramachandran;Souvik Kundu;Arnab Raha;Shamik Kundu;Deepak A. Mathaikutty;Tushar Krishna","doi":"10.1109/TVLSI.2026.3686720","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3686720","url":null,"abstract":"Structured pruning with fixed N:M sparsity ratios in large language models (LLMs) significantly constrains model expressivity, often leading to suboptimal accuracy. While supporting multiple N:M configurations can enhance representational flexibility, such a capability typically introduces substantial hardware complexity and overhead. To overcome these limitations, we first present FLOW, a flexible, layer-wise, outlier-density-aware N:M sparsity selection framework. FLOW adaptively determines the optimal N and M values per layer within a specified range by jointly considering the magnitude and distribution of outliers, thereby improving sparsity allocation and model fidelity. Extending this idea, we introduce FLOW++, which generalizes flexible N:M sparsity to the temporal domain for reasoning LLMs. FLOW++ enables temporal pruning by dynamically adapting sparsity patterns across reasoning thought types. To support efficient deployment of models with such dynamically varying sparsity patterns, we propose FlexCiM, a flexible, low-overhead, digital compute-in-memory (DCiM) architecture. FlexCiM partitions the DCiM macro into smaller submacros, which are adaptively aggregated and disaggregated through distribution and merging mechanisms for different values of N and M. We conduct experiments across different LLM families and state-space models and conclusively demonstrate that the proposed algorithm-hardware co-design framework achieves up to 36% higher accuracy, <inline-formula> <tex-math>$1.75times $ </tex-math></inline-formula> faster inference, and <inline-formula> <tex-math>$1.5times $ </tex-math></inline-formula> lower energy consumption compared to existing alternatives, establishing an effective balance between flexibility and hardware efficiency in sparse LLM inference. Code is available at: <uri>https://github.com/FLOW-open-project/FLOW</uri>","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 7","pages":"2176-2186"},"PeriodicalIF":3.2,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148515606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Booth-Based Digital Compute-in-Memory Macro With Bitwise-Efficient Multiphase Accumulation 基于位有效多相积累的数字内存中计算宏

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-07-01 Epub Date: 2026-03-04 DOI: 10.1109/TVLSI.2026.3687178

Yiying Jiang;Xiaoqin Wang;Heng You;Qiang Li;Shushan Qiao

{"title":"A Booth-Based Digital Compute-in-Memory Macro With Bitwise-Efficient Multiphase Accumulation","authors":"Yiying Jiang;Xiaoqin Wang;Heng You;Qiang Li;Shushan Qiao","doi":"10.1109/TVLSI.2026.3687178","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3687178","url":null,"abstract":"This brief presents a Booth-based all-digital SRAM compute-in-memory (CIM) macro designed for high-efficiency multiply-and-accumulate (MAC) operations in artificial intelligence applications. The architecture incorporates three key innovations: 1) a pre-encoding (PENC) scheme utilizing a Booth-based consolidated truth table, designed to reduce encoder complexity and computing unit overhead; 2) a minimalist bitwise processing technique, employing only two transistors for bit retention and shifting, aimed to minimize computational complexity within the subcomputing array; and 3) a multiphase product summation approach, integrating unified negative compensation with global sign bit expansion, intended to lower power consumption during partial product accumulation and final addition. The proposed architecture is readily adaptable to multiplications across diverse bit widths and accommodates flexible CIM array sizes, ensuring high scalability. Measurement results from a 55-nm-CMOS process demonstrate that the proposed CIM macro achieves an energy efficiency of 16.8 TOPS/W under 8b/8b MAC operations.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 7","pages":"2311-2315"},"PeriodicalIF":3.2,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148442537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 2 nA, −70 dB at 1 MHz PSRR and Trimming-Less Dual-Output CMOS Voltage Reference With Pre-Stabilization for IoT Applications 一个2 nA，−70 dB， 1 MHz PSRR和无微调双输出CMOS电压基准，具有预稳定的物联网应用

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-07-01 Epub Date: 2026-04-30 DOI: 10.1109/TVLSI.2026.3687231

Yanhan Zeng;Cailin Yu;Yanshen Luo;Jingci Yang;Yongfu Li

{"title":"A 2 nA, −70 dB at 1 MHz PSRR and Trimming-Less Dual-Output CMOS Voltage Reference With Pre-Stabilization for IoT Applications","authors":"Yanhan Zeng;Cailin Yu;Yanshen Luo;Jingci Yang;Yongfu Li","doi":"10.1109/TVLSI.2026.3687231","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3687231","url":null,"abstract":"This article presents a high power supply rejection ratio and dual-output CMOS-only voltage reference (VR) for low-power and low-voltage applications, which was manufactured in a standard 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS process. To reduce the area and improve energy efficiency, two reference voltages are obtained under a single current branch using an active load. By utilizing the significant <inline-formula> <tex-math>$Delta text {V}_{text {TH}}$ </tex-math></inline-formula> between native NMOS transistors and standard NMOS transistors, a self-biased current source was designed, achieving a power consumption of 2 nW. A pre-stabilized circuit incorporating a voltage regulator and a leakage-isolated source follower is introduced to achieve near-zero line sensitivity (LS), thereby significantly reducing the dependence of the bias current on supply voltage. Meanwhile, the leakage-isolated source follower ensures independent bias currents between two VRs in this design, resulting in better temperature characteristics. Based on the 5-chip measurement results, the average temperature coefficients of <inline-formula> <tex-math>$text {V}_{text {REF1}}$ </tex-math></inline-formula> and <inline-formula> <tex-math>$text {V}_{text {REF2}}$ </tex-math></inline-formula> are 39.45 and 136.48 ppm/°C, respectively, in a temperature range of <inline-formula> <tex-math>$- 40~{^{circ}}$ </tex-math></inline-formula>C to <inline-formula> <tex-math>$100~{^{circ}}$ </tex-math></inline-formula>C without trimming. The LS of <inline-formula> <tex-math>$text {V}_{text {REF1}}$ </tex-math></inline-formula> and <inline-formula> <tex-math>$text {V}_{text {REF2}}$ </tex-math></inline-formula> are 0.36%/V and 0.43%/V. The average PSRRs are −55 and −63 dB at 10 Hz, −43 and −38 dB at 100 Hz, and −55 and −70 dB at 1 MHz, respectively.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 7","pages":"2086-2097"},"PeriodicalIF":3.2,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148516126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Fast-Locking Phase-Locked Loop With Joint Phase and Frequency Compensation Technique 一种结合相位和频率补偿技术的快速锁相环

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-07-01 Epub Date: 2026-04-22 DOI: 10.1109/TVLSI.2026.3684335

Pin-Cheng Chen;Wei-Teng Wang;Tai-Cheng Lee

引用次数: 0

HammerBlade in Silicon: A 12-nm 2048-Core RISC-V Manycore SoC With Ruche Networks HammerBlade in Silicon: 12纳米2048核RISC-V多核SoC与Ruche网络

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-07-01 Epub Date: 2026-04-24 DOI: 10.1109/TVLSI.2026.3684311

Paul Gao;Dai Cheol Jung;Scott Davidson;Daniel Ruelas-Petrisko;Yuan-Mao Chueh;Max Ruttenberg;Kangli Li;Farzam Gilani;Dustin Richmond;Mark Oskin;Michael Bedford Taylor

{"title":"HammerBlade in Silicon: A 12-nm 2048-Core RISC-V Manycore SoC With Ruche Networks","authors":"Paul Gao;Dai Cheol Jung;Scott Davidson;Daniel Ruelas-Petrisko;Yuan-Mao Chueh;Max Ruttenberg;Kangli Li;Farzam Gilani;Dustin Richmond;Mark Oskin;Michael Bedford Taylor","doi":"10.1109/TVLSI.2026.3684311","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3684311","url":null,"abstract":"This brief presents the 99 mm<sup>2</sup>, 12-nm FinFET, 2048-core HammerBlade (HB) RISC-V manycore system-on-chip (SoC) which includes the world’s first implementation of Ruche Networks, a wire-maximal network-on-chip (NoC) topology. Prior architecture research argues for HB’s physical and logical scalability, programmability, and high density; this brief shows a concrete realization in silicon. This brief demonstrates strong results running in silicon on 2048 cores over a diverse set of representative parallelized applications, and also a world record on CoreMark (CM) score. This brief further describes in detail the silicon implementation of Ruche Networks. Operating at 1.49 GHz at 0.8 V, the NoC delivers a peak aggregate bandwidth of 2572.6 Tb/s and a bisection bandwidth of 53.2 Tb/s. The design achieves an exceptionally high routing density of 4289 bit/mm. Finally, this brief demonstrates how a small team of Ph.D. students overcame large-chip backend computer-aided design (CAD) challenges using on-chip source-synchronous interconnect (OCSSI), a globally asynchronous locally synchronous (GALS) style top-level integration methodology, combined with a turnaround-time optimized hierarchical design flow.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 7","pages":"2306-2310"},"PeriodicalIF":3.2,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148442397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information 超大规模集成电路（VLSI）系统学报

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-07-01 Epub Date: 2026-06-30 DOI: 10.1109/TVLSI.2026.3700289

引用次数: 0

Real-Time Proximity Sensing for Autonomous Systems: Custom AFE and FPGA Acceleration for FMCW Architecture 自主系统的实时接近传感：FMCW架构的自定义AFE和FPGA加速

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-07-01 Epub Date: 2026-04-14 DOI: 10.1109/TVLSI.2026.3681565

Yehyeon An;Jonghyun Kim;Seungju Lee;Jinwook Burm

{"title":"Real-Time Proximity Sensing for Autonomous Systems: Custom AFE and FPGA Acceleration for FMCW Architecture","authors":"Yehyeon An;Jonghyun Kim;Seungju Lee;Jinwook Burm","doi":"10.1109/TVLSI.2026.3681565","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3681565","url":null,"abstract":"In frequency-modulated continuous-wave (FMCW) light detection and ranging (LiDAR) systems, frequency modulation (FM) linearity and continuous-wave (CW) demodulation are the key factors determining overall performance. While most prior works focused on CPU-based linearization and decoding, this study presents a real-time FMCW architecture optimized for autonomous systems. While the system utilizes a generally robust distributed feedback (DFB) laser-based transmitter, it can be susceptible to temperature-induced frequency drift in dynamic autonomous environments. To address these fluctuations, an existing kernel-based nonlinearity tracking method was adopted and further extended into a coarse-to-fine framework for wide-range operation. The main design focus lies in the receiver, which includes a custom analog front-end (AFE) optimized for analog-to-digital converter (ADC) interfacing and multiply-accumulate (MAC) operations, along with a hardware-description-language (HDL)-based real-time decoding process. Experimental results in free space achieved a 0.15% error rate and 0.48-mm STD at 2 m, demonstrating the feasibility of the proposed architecture. In addition, an intensity measurement was conducted to verify the AFE performance.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 7","pages":"2054-2063"},"PeriodicalIF":3.2,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11481003","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148513022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Bayesian Model Calibration for Deep-Learning-Based Indirect Test of Analog Circuits 基于深度学习的模拟电路间接测试贝叶斯模型标定

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-07-01 Epub Date: 2026-04-10 DOI: 10.1109/TVLSI.2026.3680902

Jiaming Zhao;Yijiu Zhao;Shibo Chen;Jiawei Cao;Naixin Zhou;E. Shao

{"title":"Bayesian Model Calibration for Deep-Learning-Based Indirect Test of Analog Circuits","authors":"Jiaming Zhao;Yijiu Zhao;Shibo Chen;Jiawei Cao;Naixin Zhou;E. Shao","doi":"10.1109/TVLSI.2026.3680902","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3680902","url":null,"abstract":"The indirect test offers a cost-effective alternative for the specification test of analog integrated circuits (ICs). It infers high-cost specifications from low-cost measurements through a mapping function. Deep learning provides an efficient means for modeling this mapping. However, batch-to-batch variations in IC manufacturing often lead to distribution shifts, which degrade the accuracy of such data-driven techniques. To address this, we propose a transfer learning-based framework—Bayesian model calibration (BMC)—for the indirect test. During testing, a deep neural network (DNN) is trained with early data for estimation. When a new-batch arrives, a small number of samples are conventionally tested to form a calibration set. The original estimator is updated with the new dataset via a Bayesian loss function. This loss function integrates a prior term (reflecting the early data) and a likelihood term (reflecting the new data), enabling a principled tradeoff between prior knowledge and new observations. The estimator thereby adapts its parameters to improve accuracy on the new batch. Moreover, by adjusting the relative weights of the prior and likelihood terms, the extent of model update can be controlled to match the degree of distribution shift, achieving optimal calibration. The proposed approach is evaluated on a simulated operational amplifier and two commercial IC datasets to demonstrate its advantage. The BMC can improve accuracy on new batches with minimal additional samples. Moreover, by flexibly integrating the prior knowledge and new data, it outperforms baseline methods such as direct data combination (DC) and simple fine-tuning (SFT).","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 7","pages":"2274-2283"},"PeriodicalIF":3.2,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148516042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information IEEE超大规模集成电路（VLSI）系统学报

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-07-01 Epub Date: 2026-06-30 DOI: 10.1109/TVLSI.2026.3700291

引用次数: 0