IEEE Transactions on Very Large Scale Integration (VLSI) Systems最新文献

{"title":"An Efficient Sparse CNN Inference Accelerator With Balanced Intra- and Inter-PE Workload","authors":"Jianbo Guo;Tongqing Xu;Zhenyang Wu;Hao Xiao","doi":"10.1109/TVLSI.2024.3515217","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3515217","url":null,"abstract":"Sparse convolutional neural networks (SCNNs) which can prune trivial parameters in the network while maintaining the model accuracy has been proved to be an attractive approach to alleviate the heavy computation of convolutional neural networks (CNNs). However, the invalid data resulting from sparse patterns leads to unnecessary and irregular computation workload, which challenges the efficiency of the underlying hardware accelerators. Therefore, this article proposes an SCNN inference accelerator, which can deal with the imbalanced workload both intra- and interprocessing element (PE). A valid weight encoding (VWE) scheme is proposed to compress sparse weights into dense ones to alleviate the load imbalance intra-PE. Leveraging the VWE scheme, a randomized load rearrangement (RLR) method is proposed to dynamically schedule convolution kernels with similar sparsity into the same computation batch to alleviate the load imbalance inter-PEs. In addition, to reduce off-chip memory accesses, a recurrent weight stationary (RWS) dataflow is proposed, which adopts a small-batch and multichannel strategy to stack data from multiple channels within one off-chip access and let them compute simultaneously thereby enabling efficient reuse of on-chip data. Based on the proposed scheme, an efficient SCNN inference accelerator has been designed and verified on the field-programmable gate array (FPGA). Compared with state-of-the-art works, our design achieves <inline-formula> <tex-math>$1.16times $ </tex-math></inline-formula> to <inline-formula> <tex-math>$2.77times $ </tex-math></inline-formula> higher digital signal processors (DSPs) efficiency and <inline-formula> <tex-math>$1.75times $ </tex-math></inline-formula> to <inline-formula> <tex-math>$15times $ </tex-math></inline-formula> higher logic efficiency.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 5","pages":"1278-1291"},"PeriodicalIF":2.8,"publicationDate":"2024-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143875232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"VCNPU: An Algorithm-Hardware Co-Optimized Framework for Accelerating Neural Video Compression","authors":"Siyu Zhang;Wendong Mao;Zhongfeng Wang","doi":"10.1109/TVLSI.2024.3515113","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3515113","url":null,"abstract":"Video compression is essential for storing and transmitting video content. Real-time decoding is indispensable for delivering a seamless user experience. Neural video compression (NVC) integrates traditional coding techniques with deep learning, resulting in impressive compression efficiency. However, the real-time deployment of advanced NVC models encounters challenges due to their high complexity and extensive off-chip memory access. This article presents a novel NVC accelerator, called video compression neural processing unit (VCNPU), via an algorithm-hardware co-design framework. First, at the algorithmic level, a reparameterizable video compression network (RepVCN) is proposed to aggregate multiscale features and boost video compression quality. RepVCN can be equivalently transformed into a streamlined structure without extra computations after training. Second, a mask-sharing pruning strategy is proposed to compress RepVCN in the fast transform domain. It effectively prevents the destruction of sparse patterns caused by model simplification, maintaining the model capacity. Third, at the hardware level, a reconfigurable sparse computing module is designed to flexibly support sparse fast convolutions and deconvolutions of the compact RepVCN. Besides, a hybrid layer fusion pipeline is advocated to reduce off-chip data communication caused by extensive motion and residual features. Finally, based on the joint optimization of computation and communication, our VCNPU is constructed to realize adaptive adjustments of various decoding qualities and is implemented under TSMC 28-nm CMOS technology. Extensive experiments demonstrate that our RepVCN provides superior coding quality over other video compression baselines. Meanwhile, our VCNPU achieves <inline-formula> <tex-math>$6.7times $ </tex-math></inline-formula> improvements in throughput, <inline-formula> <tex-math>$2.9times $ </tex-math></inline-formula> in area efficiency, and <inline-formula> <tex-math>$4times $ </tex-math></inline-formula> in energy efficiency compared to prior video processors.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 4","pages":"1014-1027"},"PeriodicalIF":2.8,"publicationDate":"2024-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143676064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"De-Embedding Methodology to Characterize Linearity of Active Filters Under Process Variations","authors":"Hossein Eslahi;Stavroula Kapoulea;Zeeshan Ali;Mohammed Waqas Mughal;Farman Ullah;Meraj Ahmad;Martin Weides;Hadi Heidari","doi":"10.1109/TVLSI.2024.3513478","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3513478","url":null,"abstract":"This brief presents a new method to characterize the linearity of on-chip filters with accurate characterization of the filter’s transfer function (TF) in both its bandpass and stopband. Unlike conventional methods, this approach uses only one buffer, simplifying the design and improving accuracy. The filter and buffer are designed using GlobalFoundries (GF) 22-nm FDX technology, incorporating a back-gate biasing tuning mechanism in the buffer design that aims to maintain the performance of the buffer under process variation. The postlayout simulations demonstrate that the new method achieves a filter linearity of <inline-formula> <tex-math>$text {IIP3}=10.46~text {dBm}$ </tex-math></inline-formula>, with an accuracy of 99.4% compared to the standalone filter’s linearity. Similar consistency is observed across process corners.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 5","pages":"1462-1466"},"PeriodicalIF":2.8,"publicationDate":"2024-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143875166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Complementary Voltage to Time Converter With Optimized Voltage Scaling Circuit","authors":"Bo-Wei Shih;Ying-Chun Chen;Jia-Yi Lee;Woei-Luen Chen","doi":"10.1109/TVLSI.2024.3515034","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3515034","url":null,"abstract":"Delay lines often face challenges due to input-output nonlinearity and excessive voltage-to-time gain, leading to inaccurate voltage indications and a limited input voltage range. This article presents a complementary voltage-to-time converter (VTC) with an optimized voltage scaling circuit to address these issues. The complementary VTC utilizes both input-voltage-sourced and input-voltage-referenced delay lines. Although each delay line has inherent nonlinearities, the opposite signs of their respective voltage-to-time gains effectively reduce the overall nonlinearity. To further enhance performance, an optimized voltage scaling circuit is incorporated, refining nonlinearity and expanding the input voltage range. Experimental results using UMC 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m technology demonstrate that the proposed circuit achieves excellent linearity, an extended nearly rail-to-rail input voltage range, and robustness against process variations. The VTC achieves a voltage-to-time gain of 13.27 ps/mV, signal to noise and distortion ratio (SNDR) of 32.4 dB, and maintains stable dynamic performance across the working frequency band.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 5","pages":"1255-1263"},"PeriodicalIF":2.8,"publicationDate":"2024-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143875245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"GNN-Based Hardware Trojan Detection at Register Transfer Level Leveraging Multiple-Category Features","authors":"Peijun Ma;Ge Shang;Hongjin Liu;Jiangyi Shi;Weitao Pan;Yan Zhang;Yue Hao","doi":"10.1109/TVLSI.2024.3513218","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3513218","url":null,"abstract":"The existing hardware Trojan (HT) detection technology usually relies on the golden reference model. With the continuous improvement of circuit integration, the detection accuracy of traditional methods such as side-channel analysis has declined. Methods based on testability and switch probability analysis have shown high detection accuracy. However, these techniques have a limited detection scope and are generally ineffective at identifying HT where the Sandia controllability/observability analysis program (SCOAP) values or switch probabilities are similar to those of normal signals. Against this backdrop, this article proposes a detection method based on graph neural networks (GNNs), which can achieve HT detection at the register transfer level (RTL) without the golden reference model. First, the RTL code is transformed into a data flow graph (DFG), and node feature extraction and node label marking are carried out during the transformation process. To mitigate the impact of insufficient initial features on the GNN model performance, the node feature vector used in this article comprises 37-D node types and 6-D structural features such as the minimum distance from the primary input (PI) and primary output (PO), in-degree, and out-degree. Subsequently, several GNN models are built for node classification tasks. The best model achieves an average of 99.1% recall and 96.7% F1-score on the open-source dataset on the Trust-Hub platform. Compared to the state-of-the-art detection results at RTL, the F1-score in this article has increased by an average of 3.8%.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 3","pages":"831-840"},"PeriodicalIF":2.8,"publicationDate":"2024-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Guest Editorial Selected Papers From IEEE Nordic Circuits and Systems Conference (NorCAS) 2023","authors":"Jari Nurmi;Snorre Aunet;Alireza Saberkari","doi":"10.1109/TVLSI.2024.3493512","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3493512","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"32 12","pages":"2169-2172"},"PeriodicalIF":2.8,"publicationDate":"2024-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10791332","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142821186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Comparative Analysis of Low Temperature and Room Temperature Circuit Operation","authors":"Zhichao Chen;Ali H. Hassan;Rhesa Ramadhan;Yingheng Li;Chih-Kong Ken Yang;Sudhakar Pamarti;Puneet Gupta","doi":"10.1109/TVLSI.2024.3508673","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3508673","url":null,"abstract":"Low-temperature (LT) conditions can potentially lead to lower power consumption and enhanced performance in circuit operations by reducing the transistor leakage current, increasing carrier mobility, reducing wear-out, and reducing interconnect resistance. We develop PROCEED-LT, a pathfinding framework to co-optimize devices and circuits over a wide performance range. Our results demonstrate that circuit operations at LT (−196 °C) reduce power compared to room temperature (RT, 85 °C) by \u0000<inline-formula> <tex-math>$15times $ </tex-math></inline-formula>\u0000 to over \u0000<inline-formula> <tex-math>$23.8times $ </tex-math></inline-formula>\u0000 depending on performance level. Alternatively, LT improves performance by \u0000<inline-formula> <tex-math>$2.4times $ </tex-math></inline-formula>\u0000 (high-power, high-performance) \u0000<inline-formula> <tex-math>$- 7.0times $ </tex-math></inline-formula>\u0000 (low-power, low-performance) at the same power point. These gains are further improved in low-activity circuits and when using multivoltage configurations. Meanwhile, we highlight the need for improvement in \u0000<inline-formula> <tex-math>$V_{text {th}}$ </tex-math></inline-formula>\u0000 variation to leverage benefits at cryogenic temperatures.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 1","pages":"102-113"},"PeriodicalIF":2.8,"publicationDate":"2024-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Hybrid RO-TDL-Based On-Chip Voltage Monitor for FPGA Applications","authors":"Chenxi Chen;Jinhong Wang;Xueye Hu;Shubin Liu","doi":"10.1109/TVLSI.2024.3509439","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3509439","url":null,"abstract":"In recent years, field-programmable gate arrays (FPGAs) have become critical computing resources, featuring higher levels of system integration and accelerated clocking speeds. FPGA-based systems face increasing challenges in maintaining power and signal integrity. Consequently, a flexible and efficient power supply monitor is essential for evaluating the system’s performance and reliability. We propose an integrated power monitoring scheme within an FPGA, enabling real-time evaluation of power supply signal integrity. The monitor employs a hybrid structure combining a ring oscillator (RO)-based monitor and a tapped delay line (TDL)-based monitor, featuring first-order noise shaping and explicit dynamic-element matching (DEM) in its quantization. We analyze the principle of operation of the hybrid monitor and present its implementation in FPGAs. Demonstrated in an AMD Kintex-7 FPGA, tests show a voltage resolution of at least <inline-formula> <tex-math>$12.96~mu $ </tex-math></inline-formula>V and a precision of 8.03-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>V rms, and the effective bandwidth (BW) of the monitor is 10 MHz. The monitor utilizes only conventional logic resources and is delivered as a soft logic core. It can be migrated to different FPGA platforms and custom-integrated circuits with greater flexibility and integration.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 5","pages":"1384-1395"},"PeriodicalIF":2.8,"publicationDate":"2024-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143875243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information","authors":"","doi":"10.1109/TVLSI.2024.3494293","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3494293","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"32 12","pages":"C3-C3"},"PeriodicalIF":2.8,"publicationDate":"2024-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10791312","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142810598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Methodology for Datapath Energy Prediction and Optimization in Near Threshold Voltage Regime","authors":"Mahipal Dargupally;Lomash Chandra Acharya;Arvind K. Sharma;Sudeb Dasgupta;Anand Bulusu","doi":"10.1109/TVLSI.2024.3504856","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3504856","url":null,"abstract":"In this article, we propose a method for sizing an arbitrary combinational datapath to minimize its energy consumption. Our method involves deriving expressions for the components of energy consumption at both the stage and path levels. In this work, we identify overshoot energy (<inline-formula> <tex-math>$E_{text {OS}}$ </tex-math></inline-formula>) consumption as a previously unreported component contributing to energy consumption, particularly significant in the near/sub-threshold voltage regime. We determine that this <inline-formula> <tex-math>$E_{text {OS}}$ </tex-math></inline-formula> consumption is proportional to the input and output transition times and size of a logic gate at a particular stage of a datapath. We also observe that, for a given number of stages (N) and path effort, the total energy consumption is optimized when the stage effort (f) in a datapath is kept constant. Based on our observations and derivations of all the energy components and the requirement for a constant “f” in the datapath, we develop a method to minimize the energies of a logic circuit while maintaining the timing closure requirement. We determine that the non-critical paths (NCPs) must be sized to a minimum “f” while maintaining the timing requirements. We verified our models on several ISCAS and EPFL benchmark circuits with an average reduction of 28.1% (41.2%) and 19.2% (28.4%) in energy consumption [figure of merit (FoM)], respectively. The proposed methodology predicts the total energy consumption at a stage and path level of N-stage logic, with only one-time SPICE simulation on a single stage, with a maximum error of 1.3% and 1.62%, respectively, against SPICE simulations. The simulations are performed in Synopsys HSPICE environment with ST Microelectronics 65 nm CMOS and 28 nm FDSOI technology nodes, resulting in a very good agreement with the developed methodology.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 3","pages":"771-779"},"PeriodicalIF":2.8,"publicationDate":"2024-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}