IEEE Transactions on Very Large Scale Integration (VLSI) Systems最新文献_第8页

A 54.1–387.5-μW 65-nm Multimodal SoC Integrating a Custom CISC Core for Edge IoT Applications 54.1-387.5 μ w 65nm多模态SoC集成自定义CISC核心边缘物联网应用

IF 3.1 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-06-01 Epub Date: 2026-04-02 DOI: 10.1109/TVLSI.2026.3670378

Nan Wu;Shenyu Wang;Tian Tian;Zhihua Wang;Yanshu Guo;Hanjun Jiang

{"title":"A 54.1–387.5-μW 65-nm Multimodal SoC Integrating a Custom CISC Core for Edge IoT Applications","authors":"Nan Wu;Shenyu Wang;Tian Tian;Zhihua Wang;Yanshu Guo;Hanjun Jiang","doi":"10.1109/TVLSI.2026.3670378","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3670378","url":null,"abstract":"With the increasing demand for large-scale model deployment, cloud-based computing remains indispensable. However, energy and bandwidth overheads in edge-to-cloud data transmission pose significant challenges. This work presents a low-power, multimodal SoC that performs on-chip image and audio compression processing, enabling energy-efficient and low-latency cloud interaction for Internet of Things (IoT) applications. The SoC employs a two-level optimization strategy. At the microarchitecture level, a customized 16-bit fixed-length complex instruction set computing (CISC) microprocessor is introduced. Validated against a RISC-V minimal baseline RV32E equipped with equivalent peripheral engines, the proposed core achieves a <inline-formula> <tex-math>$5.06times $ </tex-math></inline-formula> reduction in core logic gate count and up to <inline-formula> <tex-math>$2.42times $ </tex-math></inline-formula> improvement in energy efficiency under iso-latency conditions. Additionally, a multipower domain strategy is adopted to further optimize energy efficiency, yielding <inline-formula> <tex-math>$5.03times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$4.13times $ </tex-math></inline-formula> improvements for image and audio modes, respectively. Fabricated in a 65-nm CMOS process, our SoC integrates both image and audio processing, achieving an ultralow power consumption of 54.1–<inline-formula> <tex-math>$387.5~mu $ </tex-math></inline-formula>W. It outperforms state-of-the-art dual-modal processors, achieving a <inline-formula> <tex-math>$2.84times $ </tex-math></inline-formula> reduction in image-processing core power and a <inline-formula> <tex-math>$12.78times $ </tex-math></inline-formula> reduction in audio compression power. Furthermore, our SoC achieves an energy efficiency of 206 pJ/bit of audio task and 15.5 pJ/pixel of image task, which offers a scalable and energy-efficient solution for versatile IoT deployments.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 6","pages":"1995-1999"},"PeriodicalIF":3.1,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148141551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Highly Reliable RRAM-Based Physical Unclonable Function With Auto-Write Technique 高可靠的基于随机存储器的物理不可克隆功能与自动写入技术

IF 3.1 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-06-01 Epub Date: 2026-03-12 DOI: 10.1109/TVLSI.2026.3670888

Li Ni;Siyuan Wu;Jinwei Pu;Shuwen Xin;Aolin Wang;Xinhui Chen;Zhengxun Lai;You Meng

{"title":"Highly Reliable RRAM-Based Physical Unclonable Function With Auto-Write Technique","authors":"Li Ni;Siyuan Wu;Jinwei Pu;Shuwen Xin;Aolin Wang;Xinhui Chen;Zhengxun Lai;You Meng","doi":"10.1109/TVLSI.2026.3670888","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3670888","url":null,"abstract":"Physical unclonable functions (PUFs) have attracted significant attention for high-security applications, particularly in the Internet of Things (IoT). While resistive random access memory (RRAM)-based PUF technology offers excellent energy efficiency and integration density, its reliability remains a major challenge. This work proposes a highly reliable RRAM-based PUF that utilizes the 4T2R cross-coupled PUF cell to extract the response. Additionally, an automatic write-back technique is introduced to enhance the initial resistance mismatch in RRAM, thereby improving the PUF reliability. Experimental results demonstrate that the proposed PUF achieves outstanding performance, with near-ideal uniqueness (50.02%), uniformity (50.11%), and robust randomness (passing NIST 800-22 tests). The design exhibits robust reliability across a wide operating range (from <inline-formula> <tex-math>$- 40~^{circ }$ </tex-math></inline-formula>C to <inline-formula> <tex-math>$120~^{circ }$ </tex-math></inline-formula>C and 0.7 to 1.4 V), achieving a bit error rate (BER) of <inline-formula> <tex-math>$lt 4.89times 10^{-7}$ </tex-math></inline-formula>. Furthermore, the energy consumption per bit is optimized to 4.8 fJ at 1.1 V, <inline-formula> <tex-math>$25~^{circ }$ </tex-math></inline-formula>C, showing its suitability for energy-constrained applications.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 6","pages":"2000-2004"},"PeriodicalIF":3.1,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148141564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Thermal Insights of 3-D BS-PDN in Cloud Server SoC Using TCAD Modeling 基于TCAD建模的云服务器SoC中3-D BS-PDN的热分析

IF 3.1 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-06-01 Epub Date: 2026-03-30 DOI: 10.1109/TVLSI.2026.3673227

Nitish Kumar;Subrat Mishra;Herman Oprins;James Myers;Julien Ryckaert;Pieter Woltgens;Dwaipayan Biswas

引用次数: 0

A 0.2%-THD Sinusoidal Signal Generator With First-Order Analog Interpolation Over More Than Three Frequency Decades for EIS Applications 一个0.2%-THD正弦信号发生器与一阶模拟插值超过三个频率十年的EIS应用

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-06-01 Epub Date: 2026-03-30 DOI: 10.1109/TVLSI.2026.3677049

Francesco Gagliardi;Andrea Ria;Massimo Piotto;Paolo Bruschi

{"title":"A 0.2%-THD Sinusoidal Signal Generator With First-Order Analog Interpolation Over More Than Three Frequency Decades for EIS Applications","authors":"Francesco Gagliardi;Andrea Ria;Massimo Piotto;Paolo Bruschi","doi":"10.1109/TVLSI.2026.3677049","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3677049","url":null,"abstract":"To develop miniaturized devices for electrical impedance spectroscopy (EIS), sinusoidal signal generators (SSGs) need to be fully integrated on chip. High spectral purity and wide frequency tunability are required. In this work, a novel approach to SSG design is proposed, leveraging first-order interpolation executed entirely in the analog domain. Compared to standard SSGs based on zero-order interpolation, lower distortion is obtained for the same clock frequency. Experimental testing of a 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS prototype, employing 32 samples for interpolation, yielded average total harmonic distortion (THD) equal to 0.225% across a 100 Hz–300 kHz frequency range, with 130-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>A consumption. Performance is consistent across different amplitude settings and process–voltage–temperature (PVT) conditions. Such findings potentially lay the groundwork for further analog-interpolation-based waveform generation solutions.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 6","pages":"1698-1711"},"PeriodicalIF":3.2,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11457804","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148514571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information 超大规模集成电路（VLSI）系统学报

IF 3.1 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-06-01 Epub Date: 2026-06-02 DOI: 10.1109/TVLSI.2026.3692258

引用次数: 0

A Multimode Built-In Self-Test Circuit for Sequential Cell Timing Characteristics Based on Digital-to-Time Converter 基于数时转换器的顺序单元时序特性多模内建自检电路

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-06-01 Epub Date: 2026-03-18 DOI: 10.1109/TVLSI.2026.3673338

Wenwen Cai;Yanhui Zhao;Zhengrui Chen;Pan Zheng;Yang Cui;Wei Zou;Xuecheng Zou;Cheng Zhuo;Li Zhang

{"title":"A Multimode Built-In Self-Test Circuit for Sequential Cell Timing Characteristics Based on Digital-to-Time Converter","authors":"Wenwen Cai;Yanhui Zhao;Zhengrui Chen;Pan Zheng;Yang Cui;Wei Zou;Xuecheng Zou;Cheng Zhuo;Li Zhang","doi":"10.1109/TVLSI.2026.3673338","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3673338","url":null,"abstract":"To address the growing challenges in high-precision timing characterization, where conventional measurement methods face limitations due to increasing process variations and multicharacteristic testing demands, this work presents an innovative multimode built-in self-test (BIST) circuit based on a digital-to-time converter (DTC). This circuit comprises a multimode design under test (DUT) module, a DTC, and a controller, enabling the simultaneous measurement of critical timing characteristics (setup/hold times and CK–Q/QN delays) across multiple sequential cells with varying trigger types and clock edges. To enhance the measurement performance, we propose a DTC architecture featuring a digitally controlled multilevel tunable delay cell within a two-stage “coarse–fine” delay chain and a multilevel switching mechanism. The BIST circuit achieves a minimum resolution of 18.7 ps, with the DTC offering a 10.5-ns dynamic range and high linearity, occupying 0.03 mm<sup>2</sup>, while the total BIST area is 0.58 mm<sup>2</sup>. Experimental results in a 180-nm process show setup/hold time measurement errors of −21 to 27 and −27 to 25 ps, respectively, and a CK–Q(QN) delay error range of −22.3 to 30.7 ps.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 6","pages":"1965-1977"},"PeriodicalIF":3.2,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148511922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Glitch-Aware Optimization of 4-2 Compressor-Based Approximate Multipliers 基于4-2压缩机近似乘法器的故障感知优化

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-06-01 Epub Date: 2026-04-14 DOI: 10.1109/TVLSI.2026.3682042

Tong Li;Tongjing Wu;Ao Liu;Honglan Jiang;Jianfei Jiang;Qin Wang;Zhigang Mao

{"title":"Glitch-Aware Optimization of 4-2 Compressor-Based Approximate Multipliers","authors":"Tong Li;Tongjing Wu;Ao Liu;Honglan Jiang;Jianfei Jiang;Qin Wang;Zhigang Mao","doi":"10.1109/TVLSI.2026.3682042","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3682042","url":null,"abstract":"Approximate multipliers have widely been used in error-resilient applications with hardware-efficient and relaxed precision requirements, such as multimedia signal processing and deep learning. Aiming to achieve improvements in power efficiency and performance, approximate multipliers are generally designed by simplifying the implementation circuits. However, the redundant switching activities (also known as glitches) due to unbalanced signal paths are seldom considered, leading to significant dynamic power. Moreover, prior approximate designs often overlook transistor sizing optimization, which limits their potential for power–delay efficiency. This article proposes a custom design and optimization framework for approximately 4-2 compressors at the structural and circuit levels, which effectively reduces glitches by balancing output delays. Based on the devised approximate 4-2 compressors, the constructed multipliers can then achieve significant reductions in the generation and propagation of spurious activities. In addition, to further reduce the dynamic power consumption, a delay-aware signal routing (DASR) strategy is introduced for interconnecting approximate compressors. The stability and efficiency of the proposed designs under varying conditions are verified by extensive simulations. The experimental results on HLMC 28-nm CMOS technology show that the approximate 4-2 compressors obtained by the proposed framework achieve 10.4%–52.1% power–delay product (PDP) reductions compared to existing approximate designs with the same accuracy, resulting in 5.20%–33.1% PDP improvements for multipliers. Moreover, the proposed optimization framework is generalizable to arbitrary approximate 4-2 compressor designs.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 6","pages":"1800-1813"},"PeriodicalIF":3.2,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148513356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Model–Hardware Co-Design of Depthwise Separable Convolution With Interlayer Pipelining for Stereo Matching 基于层间流水线的深度可分卷积立体匹配模型-硬件协同设计

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-06-01 Epub Date: 2026-04-06 DOI: 10.1109/TVLSI.2026.3678459

Zetao Guo;Yifan Wang;Wendi Sun;Jiaheng Ruan;Yukang Han;Song Chen

{"title":"Model–Hardware Co-Design of Depthwise Separable Convolution With Interlayer Pipelining for Stereo Matching","authors":"Zetao Guo;Yifan Wang;Wendi Sun;Jiaheng Ruan;Yukang Han;Song Chen","doi":"10.1109/TVLSI.2026.3678459","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3678459","url":null,"abstract":"Stereo matching is fundamental to depth perception in computer vision. While deep-learning-based stereo matching methods have significantly improved disparity map accuracy, their substantial computational demands pose challenges for deployment on resource- and power-constrained edge devices. To enable high-accuracy real-time stereo matching on such platforms, this article presents a co-design approach integrating algorithmic optimizations and hardware acceleration. First, inspired by depthwise separable convolution (DSC), a computation-driven decomposition block selection strategy is proposed to construct a lightweight stereo matching (LSM) neural network, which substantially reduces computational cost with negligible accuracy loss. Second, an optimization method for the interlayer pipelining paradigm is introduced, leveraging a DRAM access analysis model to derive optimal scheduling via dynamic programming, thereby maximizing its potential for optimizing off-chip memory access. Finally, we design a reconfigurable accelerator for interlayer pipelining that supports both single-layer and pipelined execution, achieving fine-grained load balancing via dynamic resource allocation. On the KITTI2015 dataset, the proposed LSM model yields an error rate of 2.67%. Synthesized in a 28-nm process, the accelerator processes <inline-formula> <tex-math>$960{,}times {,}544$ </tex-math></inline-formula> resolution images at 35.7 f/s. Compared with the baseline design, it delivers <inline-formula> <tex-math>$5.24times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$10.93times $ </tex-math></inline-formula> speedups, with energy reductions of 46% and 60%, respectively. Compared with state-of-the-art (SOTA) accelerators, it delivers <inline-formula> <tex-math>$1.44times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$2.00times $ </tex-math></inline-formula> speedups under comparable accuracy.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 6","pages":"1772-1785"},"PeriodicalIF":3.2,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148513359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Data-Driven Approach to Online Fault Detection in RRAM-Based Neuromorphic Hardware Using Adversarial-Inspired Test 基于数据驱动的基于ram的神经形态硬件在线故障检测方法

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-06-01 Epub Date: 2026-03-03 DOI: 10.1109/TVLSI.2026.3667040

Ming Cheng;Xiao-Chun Li;David Keezer

{"title":"A Data-Driven Approach to Online Fault Detection in RRAM-Based Neuromorphic Hardware Using Adversarial-Inspired Test","authors":"Ming Cheng;Xiao-Chun Li;David Keezer","doi":"10.1109/TVLSI.2026.3667040","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3667040","url":null,"abstract":"Resistive random access memory (RRAM)-based neuromorphic computing systems (RNCS) show great promise for low-power edge computing applications. However, hardware reliability issues in RRAM devices remain unresolved. Due to the inherent fault tolerance of RNCS, many faults do not immediately degrade system accuracy, but minor faults may pose latent risks. Meanwhile, traditional fault detection methods are insufficient for edge systems that require strict efficiency and real-time operation. This work proposes a data-driven approach based on multistage extreme gradient boosting (XGBoost) and adversarial-inspired test, specifically designed for fast online fault detection in RNCS, focusing on cell-level SAF detection under diverse fault distributions. Experiments on convolutional layers of pretrained convolutional neural network (CNN) models in RNCS demonstrate the framework’s effectiveness for real-time SAF diagnosis. Under low fault rate conditions, the proposed approach achieves an average recall of 99.8% and an average <inline-formula> <tex-math>$F1$ </tex-math></inline-formula>-score of 99.5%. In addition, the test dataset generated using the iterative fast gradient sign method (IFGSM) (adversarial-inspired test) effectively improves the distinguishability of RNCS fault-induced output signatures.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 6","pages":"1953-1964"},"PeriodicalIF":3.2,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148513683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Exploiting Hardware Nonidealities for Robust Low-Precision Ensembles on ACIM 利用硬件非理想性实现ACIM上的鲁棒低精度集成

IF 3.2 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2026-06-01 Epub Date: 2026-02-25 DOI: 10.1109/TVLSI.2026.3666118

Donghyuck Lee;Tae-Hyeon Kim

{"title":"Exploiting Hardware Nonidealities for Robust Low-Precision Ensembles on ACIM","authors":"Donghyuck Lee;Tae-Hyeon Kim","doi":"10.1109/TVLSI.2026.3666118","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3666118","url":null,"abstract":"Device variation is a fundamental challenge for analog compute-in-memory (ACIM) systems. Instead of treating it as an error, we strategically exploit it as a source of computational diversity. We harness this natural process-induced variation by programming two low-precision deep neural network (DNN) replicas onto the same ACIM chip. A soft-voting mechanism then aggregates their outputs for a more robust prediction. To quantify the system-level trade-offs, we extend the NeuroSim V1.4 framework to co-evaluate accuracy, area, latency, and energy. On VGG-8/CIFAR-10, as the conductance variation <inline-formula> <tex-math>$sigma $ </tex-math></inline-formula> increases from 0.05 to 0.25, the accuracy gain of the 4-bit ensemble over its 4-bit single-model (SM) counterpart grows from 0.46 to 3.05 percentage points (pp). Notably, at <inline-formula> <tex-math>$sigma =0.05$ </tex-math></inline-formula>, the ensemble even surpasses the zero-variation baseline by 0.303 pp. Compared to an 8-bit SM baseline, the 4-bit ensemble becomes comparable to or surpasses it for <inline-formula> <tex-math>$sigma ge 0.10$ </tex-math></inline-formula>, achieving up to 1.28 pp at <inline-formula> <tex-math>$sigma =0.25$ </tex-math></inline-formula>. Hardware evaluation using an SRAM-based ACIM architecture shows that the two-replica ensemble achieves a 9.0% smaller chip area than the 8-bit baseline, at the cost of 30% higher latency and 2.1% higher energy. We further observe consistent accuracy–overhead trends for RRAM- and FeFET-based ACIM under their respective nonideality characteristics.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 6","pages":"1889-1901"},"PeriodicalIF":3.2,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148514388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0