低纹波DIDO DC-DC混合接口与最优迟滞控制的MPPT用于TEH

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-02-26 DOI:10.1109/TVLSI.2025.3540106

Xufeng Liao;Jiabin Wang;Peiyuan Fu;Yu Du;Lianxi Liu

{"title":"低纹波DIDO DC-DC混合接口与最优迟滞控制的MPPT用于TEH","authors":"Xufeng Liao;Jiabin Wang;Peiyuan Fu;Yu Du;Lianxi Liu","doi":"10.1109/TVLSI.2025.3540106","DOIUrl":null,"url":null,"abstract":"This article proposes a dual-input-dual-output (DIDO) dc-dc hybrid interface for thermoelectric energy harvesting (TEH) applications with high efficiency and low output ripple. A load-first ordered power distributive control (OPDC) strategy is used to recycle the excess thermoelectric energy (TE) in time. Utilizing the digital adaptive <sc>on</small>-time (DAOT) technique, the output ripple can be reduced during battery (BAT) power supply. A hysteresis-controlled maximum power point tracking (MPPT) technique is proposed to track the variation of the internal resistance <inline-formula> <tex-math>$\\text {R}_{\\text {TE}}$ </tex-math></inline-formula> of the thermoelectric generator (TEG), which achieves high tracking efficiency over a wide <inline-formula> <tex-math>$\\text {R}_{\\text {TE}}$ </tex-math></inline-formula> range. By trading the tracking efficiency and loss off in the MPPT, an optimization method for hysteresis window is proposed. In addition, an analog zero-crossing detector (ZCD) without calibration is adopted to improve the end-to-end efficiency. The proposed hybrid interface is realized by 0.18-<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>m standard CMOS process with a core area of <inline-formula> <tex-math>$0.91 \\times 0.61$ </tex-math></inline-formula> mm2. Measured results show that the proposed interface can harvest TE over the <inline-formula> <tex-math>$\\text {R}_{\\text {TE}}$ </tex-math></inline-formula> variation range of 1–<inline-formula> <tex-math>$1000 \\; \\Omega $ </tex-math></inline-formula>, with a peak tracking efficiency of 99.6% and an output ripple as low as 35 mV. It also achieves a peak end-to-end efficiency of 87% and an output power range of <inline-formula> <tex-math>$1 \\; \\mu $ </tex-math></inline-formula>W −10 mW.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 6","pages":"1541-1550"},"PeriodicalIF":2.8000,"publicationDate":"2025-02-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Low-Ripple DIDO DC–DC Hybrid Interface With Optimal-Hysteresis-Controlled MPPT for TEH\",\"authors\":\"Xufeng Liao;Jiabin Wang;Peiyuan Fu;Yu Du;Lianxi Liu\",\"doi\":\"10.1109/TVLSI.2025.3540106\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article proposes a dual-input-dual-output (DIDO) dc-dc hybrid interface for thermoelectric energy harvesting (TEH) applications with high efficiency and low output ripple. A load-first ordered power distributive control (OPDC) strategy is used to recycle the excess thermoelectric energy (TE) in time. Utilizing the digital adaptive <sc>on</small>-time (DAOT) technique, the output ripple can be reduced during battery (BAT) power supply. A hysteresis-controlled maximum power point tracking (MPPT) technique is proposed to track the variation of the internal resistance <inline-formula> <tex-math>$\\\\text {R}_{\\\\text {TE}}$ </tex-math></inline-formula> of the thermoelectric generator (TEG), which achieves high tracking efficiency over a wide <inline-formula> <tex-math>$\\\\text {R}_{\\\\text {TE}}$ </tex-math></inline-formula> range. By trading the tracking efficiency and loss off in the MPPT, an optimization method for hysteresis window is proposed. In addition, an analog zero-crossing detector (ZCD) without calibration is adopted to improve the end-to-end efficiency. The proposed hybrid interface is realized by 0.18-<inline-formula> <tex-math>$\\\\mu $ </tex-math></inline-formula>m standard CMOS process with a core area of <inline-formula> <tex-math>$0.91 \\\\times 0.61$ </tex-math></inline-formula> mm2. Measured results show that the proposed interface can harvest TE over the <inline-formula> <tex-math>$\\\\text {R}_{\\\\text {TE}}$ </tex-math></inline-formula> variation range of 1–<inline-formula> <tex-math>$1000 \\\\; \\\\Omega $ </tex-math></inline-formula>, with a peak tracking efficiency of 99.6% and an output ripple as low as 35 mV. It also achieves a peak end-to-end efficiency of 87% and an output power range of <inline-formula> <tex-math>$1 \\\\; \\\\mu $ </tex-math></inline-formula>W −10 mW.\",\"PeriodicalId\":13425,\"journal\":{\"name\":\"IEEE Transactions on Very Large Scale Integration (VLSI) Systems\",\"volume\":\"33 6\",\"pages\":\"1541-1550\"},\"PeriodicalIF\":2.8000,\"publicationDate\":\"2025-02-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Very Large Scale Integration (VLSI) Systems\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10905040/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10905040/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}

引用次数: 0

摘要

本文提出了一种用于热电能量收集（TEH）应用的双输入双输出（DIDO） dc-dc混合接口，具有高效率和低输出纹波。采用负荷优先的有序功率分配控制（OPDC）策略，及时回收多余的热电能量。利用数字自适应准时（DAOT）技术，可以降低电池供电时的输出纹波。提出了一种迟滞控制的最大功率点跟踪技术（MPPT），用于跟踪热电发电机（TEG）内阻$\text {R}_{\text {TE}}$的变化，在$\text {R}_{\text {TE}}$宽范围内实现了较高的跟踪效率。通过权衡MPPT的跟踪效率和损失，提出了一种迟滞窗口的优化方法。此外，为了提高端到端效率，还采用了一种无需校准的模拟过零检测器（ZCD）。该混合接口采用0.18- $\mu $ m标准CMOS工艺实现，核心面积为$0.91 \times 0.61$ mm2。实测结果表明，该界面可在$\text {R}_{\text {TE}}$变化范围1 ～ $1000 \; \Omega $内获取TE，峰值跟踪效率为99.6% and an output ripple as low as 35 mV. It also achieves a peak end-to-end efficiency of 87% and an output power range of $1 \; \mu $ W −10 mW.

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A Low-Ripple DIDO DC–DC Hybrid Interface With Optimal-Hysteresis-Controlled MPPT for TEH

This article proposes a dual-input-dual-output (DIDO) dc-dc hybrid interface for thermoelectric energy harvesting (TEH) applications with high efficiency and low output ripple. A load-first ordered power distributive control (OPDC) strategy is used to recycle the excess thermoelectric energy (TE) in time. Utilizing the digital adaptive on-time (DAOT) technique, the output ripple can be reduced during battery (BAT) power supply. A hysteresis-controlled maximum power point tracking (MPPT) technique is proposed to track the variation of the internal resistance

$\text {R}_{\text {TE}}$

of the thermoelectric generator (TEG), which achieves high tracking efficiency over a wide

$\text {R}_{\text {TE}}$

range. By trading the tracking efficiency and loss off in the MPPT, an optimization method for hysteresis window is proposed. In addition, an analog zero-crossing detector (ZCD) without calibration is adopted to improve the end-to-end efficiency. The proposed hybrid interface is realized by 0.18-

$\mu $

m standard CMOS process with a core area of

$0.91 \times 0.61$

mm2. Measured results show that the proposed interface can harvest TE over the

$\text {R}_{\text {TE}}$

variation range of 1–

$1000 \; \Omega $

, with a peak tracking efficiency of 99.6% and an output ripple as low as 35 mV. It also achieves a peak end-to-end efficiency of 87% and an output power range of

$1 \; \mu $

W −10 mW.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.