IEEE Transactions on Very Large Scale Integration (VLSI) Systems最新文献_第9页

An Adaptive Maintain Power Signature (MPS) Scheme With Reusable Current Generator for Powered Device (PD)

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-10-28 DOI: 10.1109/TVLSI.2024.3480955

Yongyuan Li;Xuhong Yin;Wei Guo;Qiang Wu;Yongbo Zhang;Yong You;Zhangming Zhu

{"title":"An Adaptive Maintain Power Signature (MPS) Scheme With Reusable Current Generator for Powered Device (PD)","authors":"Yongyuan Li;Xuhong Yin;Wei Guo;Qiang Wu;Yongbo Zhang;Yong You;Zhangming Zhu","doi":"10.1109/TVLSI.2024.3480955","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3480955","url":null,"abstract":"The power over Ethernet (PoE) technology has gained intensive attention in networking market owing to the advantages of compactness, flexibility, and cost in application. The automatic maintain power signature (MPS) function specified by IEEE standard extracts the periodic pulsed current to enable applications requiring low power modes. However, a large driving capacity is required due to a large MPS current above 10 mA, sacrificing a certain area. This brief proposes an adaptive MPS scheme, which reuses existing class regulator and delay timer to source a pulsed MPS current to meet the MPS requirements, saving an area of 0.0104 mm2. The proposed MPS scheme has been fabricated in 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m 120-V BCD process and the area is <inline-formula> <tex-math>$1.37times 1.00$ </tex-math></inline-formula> mm2. The experimental results show that the proposed PoE interface draws a pulsed current with a period of 312 ms and 25.6% duty cycle to address the issue of MPS absence in very low-power standby modes.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 3","pages":"877-881"},"PeriodicalIF":2.8,"publicationDate":"2024-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Self-Calibrated Unified Voltage-and-Frequency Regulator System Design Based on Universal Logic Line Circuit 基于通用逻辑线路电路的自校准统一电压调频系统设计

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-10-28 DOI: 10.1109/TVLSI.2024.3466132

Jiliang Liu;Huidong Zhao;Zhi Li;Kangning Wang;Shushan Qiao

引用次数: 0

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information 电气和电子工程师学会超大规模集成 (VLSI) 系统学会论文集信息

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-10-25 DOI: 10.1109/TVLSI.2024.3474954

引用次数: 0

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information IEEE 超大规模集成 (VLSI) 系统论文集出版信息

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-10-25 DOI: 10.1109/TVLSI.2024.3474952

引用次数: 0

Electrical and Thermal Characteristics Optimization in Interposer-Based 2.5-D Integrated Circuits 基于互贴器的 2.5-D 集成电路中的电气和热特性优化

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-10-25 DOI: 10.1109/TVLSI.2024.3478846

Changle Zhi;Gang Dong;Deguang Yang;Daihang Liu;Yinghao Feng;Yang Wang;Zhangming Zhu

{"title":"Electrical and Thermal Characteristics Optimization in Interposer-Based 2.5-D Integrated Circuits","authors":"Changle Zhi;Gang Dong;Deguang Yang;Daihang Liu;Yinghao Feng;Yang Wang;Zhangming Zhu","doi":"10.1109/TVLSI.2024.3478846","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3478846","url":null,"abstract":"In this work, a comprehensive analysis and optimization method of electrical and thermal characteristics in 2.5-D integrated circuits (ICs) is performed, including rapid heat distribution modeling, integrated voltage regulator (IVR) chip modeling, and power delivery network (PDN) modeling. Based on the proposed method, chiplet placement, decoupling placement, and IVR parameter settings that compromise the total PDN impedance, IVR impedance, and thermal distribution characteristics can be obtained. First, a rapid thermal analysis method for multiple heat sources is proposed by integrating the equivalent thermal resistance method and commercial tools. The thermal method significantly improves the computational efficiency and reduces the memory usage. Then, we analyze the electrical characteristics of a typical low dropout (LDO) and model the complete 2.5-D PDN, including interposers, chiplets, IVRs, through-silicon vias (TSVs), bumps, decoupling capacitors, and other components. The electrical and thermal problems in the 2.5-D system are formulated and a Metropolis rule-based algorithm is used to derive optimal solutions. Finally, the optimal placement schemes and parameter settings are iterated under different constraints. This method allows for the adjustment of target impedance, noise current, thermal limit, and other constraints based on varying practical situations. In the time-domain analysis, it can be found that the capacitance value is reduced while maintaining the power supply performance. With high accuracy in thermal and electrical modeling, this work provides an in-depth reference for the co-design of chiplet-based 2.5-D ICs.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 3","pages":"627-637"},"PeriodicalIF":2.8,"publicationDate":"2024-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Area/Power-Efficient Noise-Shaping SAR ADC for Implantable Biosensor Applications Featuring a Unique Auxiliary Feedback Loop

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-10-23 DOI: 10.1109/TVLSI.2024.3477717

Weihao Wang;Kong-Pang Pun

{"title":"An Area/Power-Efficient Noise-Shaping SAR ADC for Implantable Biosensor Applications Featuring a Unique Auxiliary Feedback Loop","authors":"Weihao Wang;Kong-Pang Pun","doi":"10.1109/TVLSI.2024.3477717","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3477717","url":null,"abstract":"Wide bandwidth and power-area efficient front-ends are required in emerging implantable biosensor applications, e.g., wireless artificial vision systems for the limited vision. This work presents a low-power 0.031 mm<inline-formula> <tex-math>$^{2}~3$ </tex-math></inline-formula>-MHz bandwidth noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) tailored for implantable biosensor applications. A highly energy- and area-efficient reset-free residue-processing scheme is proposed. This scheme facilitates noise transfer function (NTF) optimization by enabling control over complex poles. It establishes a unique auxiliary feedback path from the infinite impulse response (IIR) back to the finite impulse response (FIR) by eliminating the need for the FIR filter’s reset phase. This auxiliary feedback loop, which could not be achieved in previous FIR-IIR structures, is a key enabler for achieving high energy efficiency and design flexibility. The in-band quantization noise suppression is boosted by the proposed complex conjugate poles optimization technique, while a low <inline-formula> <tex-math>$kT/C$ </tex-math></inline-formula> input-referred noise has resulted. The prototype, fabricated in 65-nm CMOS technology with a 7-bit digital-to-analog converter (DAC), consumes <inline-formula> <tex-math>$370~mu $ </tex-math></inline-formula>W from a 1-V supply and occupies an active area of only <inline-formula> <tex-math>$0.17times 0.18$ </tex-math></inline-formula> mm (0.031-mm2). Operating at an 80-MHz oversampling frequency, the proposed ADC achieves a signal-to-noise and distortion ratio (SNDR) of 70.2 dB over a 3 MHz bandwidth, demonstrating its small area, high efficiency, and high performance for implantable biosensor applications that require high data rates.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 3","pages":"685-696"},"PeriodicalIF":2.8,"publicationDate":"2024-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 4.2-to-0.5-V, 0.8-μA–0.8-mA, Power-Efficient Three-Level SIMO Buck Converter for a Quad-Voltage RISC-V Microprocessor 一种用于四电压RISC-V微处理器的4.2- 0.5 v, 0.8 μA - 0.8 ma，节能的三电平SIMO降压转换器

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-10-23 DOI: 10.1109/TVLSI.2024.3477632

Dongkwun Kim;Zhaoqing Wang;Paul Xuanyuanliang Huang;Pavan Kumar Chundi;Suhwan Kim;Andrés A. Blanco;Ram K. Krishnamurthy;Mingoo Seok

{"title":"A 4.2-to-0.5-V, 0.8-μA–0.8-mA, Power-Efficient Three-Level SIMO Buck Converter for a Quad-Voltage RISC-V Microprocessor","authors":"Dongkwun Kim;Zhaoqing Wang;Paul Xuanyuanliang Huang;Pavan Kumar Chundi;Suhwan Kim;Andrés A. Blanco;Ram K. Krishnamurthy;Mingoo Seok","doi":"10.1109/TVLSI.2024.3477632","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3477632","url":null,"abstract":"This article presents a Li-ion battery-compatible single-inductor-multiple-output (SIMO) buck converter that fulfills the power management need of an integrated sub-mW RISC-V microprocessor. The proposed converter can directly take a 4.2-V battery voltage and produce four power rails ranging from 1.8 V for I/O to 0.5 V for the processor core. The three-level input stage is chosen to reduce the inductor ripple size and switching loss, thus increasing power conversion efficiency (PCE). In addition, the fully digital implementation using novel domino flash analog-digital converters (ADCs) enables low static current. Also, pulse frequency modulation (PFM) results in a wide dynamic range. The proposed three-level SIMO converter has been prototyped in a 65-nm CMOS technology with the 32-bit RISC-V processor. Measurement results show that the converter achieves a \u0000<inline-formula> <tex-math>$1000times $ </tex-math></inline-formula>\u0000 load current range (\u0000<inline-formula> <tex-math>$0.8~mu $ </tex-math></inline-formula>\u0000A–0.8 mA) to support the active or sleep modes of the processor. The converter marks the PCE of 56.2%–72.8%. Compared to the ideal buck-low-dropout voltage regulator (LDO) architecture (LDO-only), it improves the PCE by 23.8% (46.4%).","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 1","pages":"193-206"},"PeriodicalIF":2.8,"publicationDate":"2024-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Improving a Ka-Band Integrated Balanced Power Amplifier Performance by Compensating Quadrature Hybrid Mismatch Effects 通过补偿正交杂化失配效应改善ka波段集成平衡功率放大器性能

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-10-21 DOI: 10.1109/TVLSI.2024.3475810

Jere Rusanen;Negar Shabanzadeh;Aarno Pärssinen;Timo Rahkonen;Janne P. Aikio

{"title":"Improving a Ka-Band Integrated Balanced Power Amplifier Performance by Compensating Quadrature Hybrid Mismatch Effects","authors":"Jere Rusanen;Negar Shabanzadeh;Aarno Pärssinen;Timo Rahkonen;Janne P. Aikio","doi":"10.1109/TVLSI.2024.3475810","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3475810","url":null,"abstract":"This article presents an integrated quadrature balanced power amplifier (PA) operating at a 26-GHz frequency range and techniques to mitigate the frequency-dependent amplitude response of quadrature hybrids used in the balanced amplifier design. The overall structure consists of two stacked pseudo-differential PAs and transformer-based quadrature hybrids designed with 22-nm CMOS FDSOI. Two techniques to compensate frequency-dependent amplitude response of the quadrature hybrid when operating away from the center frequency are proposed. The first one involves a dual input drive and the second one involves asymmetric biasing. With distortion contribution analysis, it is shown that asymmetric biasing compensates quadrature hybrid asymmetry but also produces mutually compensating third-order nonlinearity, resulting in improved linearity. Measurements with continuous wave (CW) and high dynamic range fifth generation (5G) modulated signal demonstrate that the described techniques improve output power that can be reached within the linearity specifications when operating away from the center frequency.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"32 12","pages":"2198-2209"},"PeriodicalIF":2.8,"publicationDate":"2024-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10726609","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142821280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Novel Prediction-Based Two-Tiered ECC for Mitigating SWD Errors in HBM 一种新的基于预测的双层ECC减轻HBM中SWD误差

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-10-21 DOI: 10.1109/TVLSI.2024.3474791

Youngki Moon;Seung Ho Shin;Seokjun Jang;Duyeon Won;Sungho Kang

{"title":"A Novel Prediction-Based Two-Tiered ECC for Mitigating SWD Errors in HBM","authors":"Youngki Moon;Seung Ho Shin;Seokjun Jang;Duyeon Won;Sungho Kang","doi":"10.1109/TVLSI.2024.3474791","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3474791","url":null,"abstract":"Errors emerge as a major issue in the reliability of dynamic random access memory (DRAM). To enhance reliability, a two-tiered error correction code (ECC) architecture that comprises on-die ECC (OD-ECC) and system ECC (S-ECC) is adopted as a part of the standard for state-of-the-art high-bandwidth memory (HBM). However, conventional ECCs are insufficient to mitigate malfunctions of subwordline drivers (SWDs), a primary cause of errors. Moreover, the efficient co-design of two-tiered ECCs has not been sufficiently studied. To address these issues without increasing the size of check bits, this article proposes a two-tiered ECC architecture comprising an OD-ECC based on prediction and an S-ECC with data deinterleaving. The proposed OD-ECC predicts the SWD errors by leveraging the detection capabilities of two interleaved Reed-Solomon (RS) engines. In addition, the proposed S-ECC not only preserves strong error detection capability but also masks the misprediction effect of OD-ECC, where data deinterleaving renders additional errors caused by misprediction of OD-ECC to be bounded in the detectable range of the employed cyclic redundancy check (CRC). The experimental results demonstrate that the proposed two-tiered ECC can significantly enhance the error correction capability for SWD errors while maintaining the correction capability for other types of errors.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 2","pages":"488-498"},"PeriodicalIF":2.8,"publicationDate":"2024-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142993410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Designing Precharge-Free Energy-Efficient Content-Addressable Memories 设计无预充电的高能效内容可寻址存储器

IF 2.8 2区工程技术

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-10-18 DOI: 10.1109/TVLSI.2024.3475036

Ramiro Taco;Esteban Garzón;Robert Hanhan;Adam Teman;Leonid Yavits;Marco Lanuzza

{"title":"Designing Precharge-Free Energy-Efficient Content-Addressable Memories","authors":"Ramiro Taco;Esteban Garzón;Robert Hanhan;Adam Teman;Leonid Yavits;Marco Lanuzza","doi":"10.1109/TVLSI.2024.3475036","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3475036","url":null,"abstract":"Content-addressable memory (CAM) is a specialized type of memory that facilitates massively parallel comparison of a search pattern against its entire content. State-of-the-art (SOTA) CAM solutions are either fast but power-hungry (NOR CAM) or slow while consuming less power (nand CAM). These limitations stem from the dynamic precharge operation, leading to excessive power consumption in NOR CAMs and charge-sharing issues in NAND CAMs. In this work, we propose a precharge-free CAM (PCAM) class for energy-efficient applications. By avoiding precharge operation, PCAM consumes less energy than a NAND CAM, while achieving search speed comparable to a NOR CAM. PCAM was designed using a 65-nm CMOS technology and comprehensively evaluated under extensive Monte Carlo (MC) simulations while taking into account layout parasitics. When benchmarked against conventional NAND CAM, PCAM demonstrates improved search run time (reduced by more than 30%) and 15% less search energy. Moreover, PCAM can cut energy consumption by more than 75% when compared to conventional NOR CAM. We further extend our analysis to the application level, functionally evaluating the CAM designs as a fully associative cache using a CPU simulator running various benchmark workloads. This analysis confirms that PCAMs represent an optimal energy-performance design choice for associative memories and their broad spectrum of applications.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"32 12","pages":"2303-2314"},"PeriodicalIF":2.8,"publicationDate":"2024-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10723100","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142821282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0