IEEE Transactions on Very Large Scale Integration (VLSI) Systems最新文献

{"title":"RLRM: Reinforcement Learning-Based Routing for Ring-Augmented Mesh NoC","authors":"Juan Fang;Jingming Guo;Yubin He;Qi Ming","doi":"10.1109/TVLSI.2026.3664149","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3664149","url":null,"abstract":"Modern multicore processors increasingly rely on network-on-chip (NoC) architectures to support high-bandwidth and low-latency communication. Traditional mesh-based NoC topologies suffer from uneven load distribution, with central router nodes frequently becoming congestion hot spots. The existing approaches mainly focus on introducing bypass links or independent ring interconnects. However, bypass links can only alleviate congestion between fixed routers, and routers not included in the ring still rely on conventional mesh forwarding, limiting the overall performance improvement. To address these challenges, this article proposes a reinforcement learning-based routing for ring-augmented mesh NoC (RLRM) to improve communication efficiency in multicore processors. First, we design a ring-augmented <inline-formula> <tex-math>$8times 8$ </tex-math></inline-formula> mesh topology that integrates horizontal and vertical ring interconnects to achieve balanced load distribution and mitigate congestion hotspots. Second, we equip each router with a topology-aware reinforcement learning (RL) agent that dynamically selects paths based on congestion conditions, thereby proactively avoiding performance bottlenecks. Extensive experiments demonstrate that the proposed solution provides a scalable and efficient architecture for high-performance computing and multicore NoC systems. Experimental results under realistic benchmark traffic patterns show that RLRM reduces average latency by 22.78% compared to conventional mesh and static hybrid routing schemes.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 6","pages":"1916-1929"},"PeriodicalIF":3.2,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148515652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"FANE: FPGA-Based FP8 Approximate Neural Network Engine","authors":"Han Bao;Shidi Tang;Jingdong Li;Ahmed Sadaqa;Ruiqi Chen;Ming Ling;Bruno da Silva","doi":"10.1109/TVLSI.2026.3677683","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3677683","url":null,"abstract":"The 8-bit floating-point (FP8) format has gained growing interest in neural networks (NNs) for its superior dynamic range over traditional INT8. However, multiply-accumulate (MAC) operations remain a major source of power consumption during inference of NNs, which makes DSP-free design important, especially for edge FPGAs with few or no DSPs. Therefore, this brief presents FPGA-based FP8 approximate neural network engine (FANE), an FPGA-based approximate NN engine for FP8. We first introduce a novel approximation method that replaces the multiplications by linear additions. This approximate method reduces power consumption while maintaining high accuracy, outperforming the latest FP8 approximate multiplier by 53.15%. Based on this design, we construct an FP8 MAC unit and integrate it into both a convolution engine and a matrix–vector multiplication (MVM) unit. Finally, we integrate our design into a large language model (LLM). The result shows 61.5% higher efficiency (TOPS/W) than the previous design, demonstrating the superiority of FANE in terms of performance and power efficiency. The code of FANE is available at <uri>https://gitlab.com/etrovub/embedded-systems/publications/fane-fpga-based-fp8-approximate-neural-network-engine</uri>","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 6","pages":"2015-2019"},"PeriodicalIF":3.1,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148141583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Metal Stack Exploration for Front- Versus Back- Side Clock and Signal Allocation for Advanced CMOS PPA Improvements","authors":"Nishant Gupta;Sirish Oruganti;Sai Subrahmanya Teja Nibhanupudi;Anup Ashok Kedilaya;Xiuhao Zhang;Jaydeep P. Kulkarni","doi":"10.1109/TVLSI.2026.3678304","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3678304","url":null,"abstract":"This study explores the potential of back-side contact (BSC) technology for enhancing power, performance, and area (PPA) in integrated circuits (ICs). Through metal stack exploration experiments on a 32-bit RISC-V core, the research demonstrates significant PPA gains by optimizing front- and back-side metal (BSM) stack and layer purpose allocation. Key findings include a 2.7% power reduction per added back-side layer for clock routing, a 5.5% frequency improvement with combined front- and back-side clock routing, and up to 14.71% power reduction or 10% frequency increase through metal stack optimization for low-power and high-performance targets, respectively. A similar study on an FPGA was also conducted by optimizing the layer stack configuration to achieve maximum frequency gains of 55.34% or 8.95% in total power consumption, respectively, compared to the baseline of an eight front-side-only layer stack configuration.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 6","pages":"1848-1856"},"PeriodicalIF":3.2,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148511361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"HiRe: A Hierarchical Reconfigurable Architecture for Large-Scale Multichiplet DNN Accelerators","authors":"Zhihong Chen;Jinming Zhang;Dongxu Lyu;Hao Chen;Jianfei Jiang;Weiguang Sheng;Chen Zhang;Guanghui He","doi":"10.1109/TVLSI.2026.3676552","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3676552","url":null,"abstract":"Multichiplet deep neural network (DNN) accelerators have evolved as promising modular solutions, offering enhanced performance, scalability, and cost-effectiveness. These architectures, however, suffer from the escalating communication bottleneck with increasing scale, primarily stemming from rising hop count and worsening link underutilization. The bottleneck is exacerbated by conventional fixed interconnection networks’ nonadaptability to diverse DNN dataflows. Moreover, an efficient routing tailored for large-scale networks with deadlock-freedom is needed for performance. To address these scalability challenges, leveraging the low-latency links and abundant interconnection resources with reconfigurability in the active interposer, we propose HiRe, a hierarchical reconfigurable network-routing co-design architecture for large-scale multichiplet DNN accelerators. The architecture introduces reconfigurable nodes (RNs) across on-chip and interchiplet hierarchical networks, enabling dynamic bypassing and network reconfiguration. Based on the network, it incorporates an efficient deadlock-free routing that combines simulated annealing (SA)-based communication scheduling with greedy path selection. Through the network-routing co-design, HiRe reduces the hop count and enhances the link utilization. The HiRe architecture is implemented and synthesized in a 55-nm CMOS process. Experimental results demonstrate that HiRe achieves a 14.3%–45.2% EDP reduction and a 14.1%–35.0% latency reduction compared to state-of-the-art (SOTA) innovations, effectively mitigating the large-scale communication bottleneck.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 6","pages":"1736-1749"},"PeriodicalIF":3.2,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148513353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"DayPQ: Dynamic Layerwise Pruning and Quantization for LLM Inference Acceleration","authors":"Yongchao Xu;Mingxuan Li;Ziying Zhuo;Qinzhe Zhi;Tianyu Jia;Meiqi Wang","doi":"10.1109/TVLSI.2026.3666193","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3666193","url":null,"abstract":"The deployment of the prevailing large language models (LLMs) on resource-constrained hardware faces critical challenges due to their massive computational and memory requirements. Pruning and quantization (PQ), as two predominant techniques for LLM acceleration, face the challenge of fully preserving model capabilities while achieving significant acceleration in practice. Static PQ irreversibly discards potentially critical parameters and degrades precision across diverse inputs, which must be compensated through fine-tuning. Dynamic PQ preserves accuracy but incurs prohibitive hardware overhead and additional latency from runtime adaptations. Achieving low-latency and overhead-efficient dynamic PQ requires the co-design of adaptive compression tightly integrated with hardware. In this work, we present DayPQ, an algorithm-hardware co-optimization technique for efficient LLM inference: self-adaptive norm-based pruning and bias-shifting FP8 quantization at the algorithm level, synergized with a multiplication-free shift–add PE array and switchable dataflow at the hardware level, achieving dynamic acceleration with the negligible accuracy loss and zero additional latency. DayPQ enables adaptive PQ by intrinsically exploiting normalization operations from the model’s inference process instead of extra operations. Simultaneously, it establishes dynamic orthogonality between sparsity and quantization, where these dual compression mechanisms synergistically enhance the redundancy reduction beyond mere additive effects of independent operations. Our evaluation shows that DayPQ obtains an average <inline-formula> <tex-math>$3.13times $ </tex-math></inline-formula> higher energy efficiency and <inline-formula> <tex-math>$2.03times $ </tex-math></inline-formula> performance boost than three state-of-the-art (SOTA) accelerators.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 6","pages":"1712-1722"},"PeriodicalIF":3.2,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148514520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Hardware Acceleration of Kolmogorov–Arnold Network (KAN) in Large-Scale Systems","authors":"Wei-Hsing Huang;Jianwei Jia;Yuyao Kong;Faaiq Waqar;Tai-Hao Wen;Meng-Fan Chang;Shimeng Yu","doi":"10.1109/TVLSI.2026.3673356","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3673356","url":null,"abstract":"Recent developments have introduced Kolmogorov– Arnold networks (KANs), an innovative architectural paradigm capable of replicating conventional deep neural network (DNN) capabilities while utilizing significantly reduced parameter counts through the employment of parameterized B-spline functions incorporating trainable coefficients. Nevertheless, the B-spline functional components inherent to KAN architectures introduce distinct hardware acceleration complexities. While B-spline function evaluation can be accomplished through lookup table (LUT) implementations that directly encode functional mappings, thus minimizing computational overhead, such approaches continue to demand considerable circuit infrastructure, including LUTs, multiplexers, decoders, and associated components. This work presents an algorithm-hardware co-design approach for KAN acceleration. At the algorithmic level, techniques include alignment–symmetry and PowerGap KAN hardware-aware quantization, KAN sparsity-aware mapping strategy, and circuit-level techniques include N:1 time modulation dynamic voltage input generator with analog-compute-in-memory (ACIM) circuits. Furthermore, this work conducts comprehensive evaluations on large-scale KAN networks to validate the proposed methodologies. Nonideality factors, including partial sum deviations arising from process variations, have been evaluated with the statistics measured from the TSMC 22-nm RRAM-ACIM prototype chips. Utilizing optimally determined KAN hyperparameters in conjunction with circuit optimizations implemented and evaluated at the 22-nm technology node, despite the model sizes for large-scale tasks in this work increasing by 435 K<inline-formula> <tex-math>$times $ </tex-math></inline-formula> to 756 K<inline-formula> <tex-math>$times $ </tex-math></inline-formula> compared to tiny-scale tasks in previous work, the area overhead increases by only 26 K<inline-formula> <tex-math>$times $ </tex-math></inline-formula> to 40 K<inline-formula> <tex-math>$times $ </tex-math></inline-formula>, with power consumption rising by merely <inline-formula> <tex-math>$48times $ </tex-math></inline-formula> to <inline-formula> <tex-math>$93times $ </tex-math></inline-formula>, while accuracy degradation remains minimal at 0.11%–0.22%, thereby demonstrating the scaling potential of our proposed architecture.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 6","pages":"1723-1735"},"PeriodicalIF":3.2,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148513357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"ParaPM: Efficient Hardware Accelerator for Postquantum Signature With High-Performance Polynomial Multiplier","authors":"Yumeng Zhao;Gaoming Du;Xiaolei Wang;Yongsheng Yin;Duoli Zhang;Zhenmin Li","doi":"10.1109/TVLSI.2026.3678026","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3678026","url":null,"abstract":"During the Institute of Standards and Technology (NIST) postquantum cryptography standardization process, the lattice-based Dilithium scheme was selected as one of the three third-round finalists for digital signature algorithms. Although numerous hardware implementations of Dilithium have been proposed, there remains substantial room for performance optimization, particularly in terms of computational speed. In this work, we target the two most time-consuming operations, namely the coefficient generation and polynomial multiplication. We propose a high-speed hardware architecture that fully exploits hardware parallelism. Our design introduces a fully pipelined radix-2 multipath delay commutator (R2MDC) structure supporting both NTT and inverse NTT (INTT) modes, a throughput-matched polynomial multiplier enabling on-the-fly pointwise multiplication (PWM) without buffering, and a low-resource Keccak. These optimizations collectively eliminate the throughput mismatch bottleneck and maximize hardware utilization through task-level parallelism. We implement coefficient generation, signing, and verification for three security levels on the A7 and Z7 platforms. Experimental results demonstrate that our current design achieves the optimal area-time product (ATP) across all three security levels.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 6","pages":"1857-1866"},"PeriodicalIF":3.2,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148513678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Fast Convergence Background Calibration Technique for Gain Nonlinearity in Pipeline ADCs","authors":"Qiao Wang;Xizhu Peng;Zhifei Lu;Yutao Peng;He Tang","doi":"10.1109/TVLSI.2026.3678216","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3678216","url":null,"abstract":"A novel background calibration technique for gain nonlinearity in pipeline analog-to-digital converters (ADCs) with fast convergence is presented in this brief. The proposed method leverages dual-comparator parallel calibration (DCPC) and multiplying digital-to-analog converter (MDAC) dither injection to extract inter-stage gain error (IGE), gain nonlinearity, and capacitor mismatch. This method employs a large dither window and a low-complexity algorithm to achieve fast convergence. Compared with prior dither-based calibration works, this work avoids introducing additional residue signal swing increment, thereby relaxing the design requirements of the residue amplifier (RA). Simulations demonstrate that the calibration technique improves the signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) by 30.5 and 36.6 dB, respectively, in a 14-bit 1-Gsps pipeline ADC affected by IGE, gain nonlinearity, capacitor mismatch, and −74 dB thermal noise. The convergence requires only <inline-formula> <tex-math>$1.25{,}times{,}10^{6}$ </tex-math></inline-formula> conversions, representing an at least eightfold improvement over prior art.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 6","pages":"2020-2024"},"PeriodicalIF":3.1,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148141561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Compact Inverter-Based Neural Amplifier With Local and System Dual CMFB Loops Through Paralleled Pseudo Transconductors","authors":"Longbin Zhu;Wenjie Wang;Zhijun Zhou;Keping Wang","doi":"10.1109/TVLSI.2026.3667606","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3667606","url":null,"abstract":"This brief presents a CMOS inverter (INV)-based amplifier with local and system dual common-mode feedback (CMFB) loops through paralleled pseudo transconductors (PTs) for multichannel neural signal recording. The PT-INV forms a DC-coupled input to ensure a high input impedance, and local and system dual CMFB loops are introduced through the paralleled PT terminals of the INV. The local CMFB (L-CMFB) with the capacitor-reused topology not only reduces the die area and increases the differential-mode (DM) gain but also reduces the common-mode (CM) gain. The system CMFB (S-CMFB) loop detects the multiple CM outputs, and further increases the overall CMRR. The proposed PT-INV based instrumentation amplifiers (IAs) with dual CMFB loops are fabricated in a 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS process, and an overall CMRR of 87 dB is achieved with a compact single-channel core area of 0.02 mm².","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 6","pages":"1991-1994"},"PeriodicalIF":3.1,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148141567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information","authors":"","doi":"10.1109/TVLSI.2026.3692260","DOIUrl":"https://doi.org/10.1109/TVLSI.2026.3692260","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 6","pages":"C2-C2"},"PeriodicalIF":3.2,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11547351","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148512415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}