A Laddered-Inverter Nonoverlapping Clock Generator

Abstract

This article presents a new and novel nonoverlapping clock (NOC) generator based on a laddered inverter (LI) circuit. Unlike conventional approaches, the proposed NOC combines the clock generation and pulsewidth-modulation (PWM) circuit into one integrated architecture, offering lower power consumption, smaller area, and a more robust solution. Furthermore, the proposed NOC offers an inherent guarantee of the nonoverlap (dead time) between the output signals thanks to the guaranteed monotonicity of the LI circuit, thus offering a layout-agnostic design. The proposed NOC can also offer dead-time reconfigurability with the help of multiplexers, allowing both calibration and fine-tuning of the dead times to meet specific requirements. We provide a comprehensive assessment of the proposed NOC through simulation and measurement results in 65-nm CMOS. Measured results show that the proposed NOC consumes $1~\mu $ W at 5 MHz with a 1-V supply, achieving more than $10\times $ lower power consumption and 25% smaller area compared to the conventional NOC circuit. The proposed NOC demonstrates the capability to generate waveforms with frequencies up to 3.5 GHz at a 1.2-V supply, as validated through simulations.