A 25-GS/s 8-bit Current-Steering DAC With ADC-Based Duty-Cycle Detection in 40-nm CMOS

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-02-17 DOI:10.1109/TVLSI.2025.3525706

Xing Li;Lei Zhou;Xuan Guo;Hanbo Jia;Danyu Wu;Jin Wu;Xinyu Liu

引用次数: 0

Abstract

This brief presents a current-steering 25-GS/s 8-bit digital-to-analog converter (DAC) based on a 40-nm CMOS technology. The DAC employs a dual-edge sampling (DES) architecture to reduce the requirement of main clock frequency, optimizing switching noise and improving power efficiency. DES is sensitive to the clock duty cycle. To minimize the image tones and performance degradation caused by duty-cycle errors, a single-slope analog-to-digital converter (ADC)-based duty-cycle detection and correction scheme is proposed, achieving closed-loop background calibration. A T-coil output network is used to extend the bandwidth. The proposed DAC achieves a spurious-free dynamic range (SFDR) of >40 dBc up to the Nyquist frequency and a >12-GHz output bandwidth with sinc roll-off compensation. The active power consumption is about 272 mW under 1.8-/0.9-/−1.8-V power supply.

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基于adc的40纳米CMOS占空比检测的25-GS/s 8位电流转向DAC

本文介绍了一种基于40纳米CMOS技术的电流转向25-GS/s 8位数模转换器（DAC）。DAC采用双边缘采样（DES）架构，降低了对主时钟频率的要求，优化了开关噪声，提高了功耗效率。DES对时钟占空比敏感。为了最大限度地降低占空比误差引起的图像色调和性能下降，提出了一种基于单斜率模数转换器（ADC）的占空比检测和校正方案，实现了闭环背景校准。使用t圈输出网络扩展带宽。所提出的DAC在奈奎斯特频率下实现了> - 40dbc的无杂散动态范围（SFDR）和带自滚降补偿的> - 12ghz输出带宽。在1.8-/0.9-/−1.8 v电源下，有功功耗约为272 mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.