SRAM BL Predriven Write Operation With Row and Voltage Auto-Tracking Replica BL in Resistance-Dominated Technology Nodes

Abstract

In this article, we analyze the effect of the bitline (BL) predriven write operation in alleviating static random access memory (SRAM) writability degradation caused by BL resistance ( $R_{\text {BL}}$ ). In BL predriven write operation, BL is fully driven to the ground voltage regardless of $R_{\text {BL}}$ and the cell is written by a strong instantaneous peak write current ( $I_{\text {write,peak}}$ ) between the cell and BL. The writability yield of BL predriven write operation in the resistance-dominated technology nodes can, thus, be significantly improved. In addition, the row and voltage auto-tracking replica BL (RVAT-RepBL) is proposed to generate BL predriven time ( $T_{\text {pre}}$ ) for BL predriven write operation. In the proposed RVAT-RepBL, $T_{\text {pre}}$ is generated by automatically tracking the variation in the number of rows per BL, $R_{\text {BL}}$ , and the supply voltage ( $V_{\text {DD}}$ ). In order to verify the effect of BL predriven write operation, the test chip was fabricated on 28-nm CMOS technology, and the poly resistor arrays were inserted to the cell array to reflect the interconnect resistance in the advanced technology nodes. BL predriven write operation has a higher writability yield and a wider operating $V_{\text {DD}}$ than the conventional write operation. In addition, when the word line (WL) repeater is applied, the results of BL predriven write operation show that the writability yield of BL predriven write operation is further improved as $I_{\text {write,peak}}$ increases with the improvement of WL rising slope.