发布求助
文献互助 智能选刊 最新文献

2022 IEEE International Memory Workshop (IMW)最新文献

筛选
英文 中文
A novel 3D 1T1R RRAM architecture for memory-centric Hyperdimensional Computing 一种新颖的3D 1T1R RRAM架构，用于以内存为中心的超维计算
2022 IEEE International Memory Workshop (IMW) Pub Date : 2022-05-01 DOI: 10.1109/IMW52921.2022.9779306
T. Dubreuil, P. Amari, S. Barraud, J. Lacord, E. Esmanhotto, V. Meli, S. Martin, N. Castellani, B. Previtali, François Andrieu
{"title":"A novel 3D 1T1R RRAM architecture for memory-centric Hyperdimensional Computing","authors":"T. Dubreuil, P. Amari, S. Barraud, J. Lacord, E. Esmanhotto, V. Meli, S. Martin, N. Castellani, B. Previtali, François Andrieu","doi":"10.1109/IMW52921.2022.9779306","DOIUrl":"https://doi.org/10.1109/IMW52921.2022.9779306","url":null,"abstract":"In this work, we present a novel 3D 1T1R RRAM architecture. Thanks to a proper connection of SourceLines (SLs), BitLines (BLs), and WordLines (WLs), we propose to implement a memory-centric hyperdimensional computing (HDC) algorithm for language recognition. SPICE simulations validate the main HD vector operations (i.e generation of seed hypervectors, XNOR, SHIFT, etc.) with an efficiency reaching up to 95%. On this basis, we demonstrated a first experimental implementation of AND operation with a 1kb RRAM array. Finally, we discuss how each part of this 3D structure integrates and links each building block of HDC algorithm with a high level of parallelism.","PeriodicalId":132074,"journal":{"name":"2022 IEEE International Memory Workshop (IMW)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114942499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
[Copyright notice] (版权)
2022 IEEE International Memory Workshop (IMW) Pub Date : 2022-05-01 DOI: 10.1109/imw52921.2022.9779249
{"title":"[Copyright notice]","authors":"","doi":"10.1109/imw52921.2022.9779249","DOIUrl":"https://doi.org/10.1109/imw52921.2022.9779249","url":null,"abstract":"","PeriodicalId":132074,"journal":{"name":"2022 IEEE International Memory Workshop (IMW)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116220146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Persistent xSPI STT-MRAM with up to 400MB/s Read and Write Throughput 具有高达400MB/s读写吞吐量的持久xSPI STT-MRAM
2022 IEEE International Memory Workshop (IMW) Pub Date : 2022-05-01 DOI: 10.1109/IMW52921.2022.9779276
S. Alam, D. Houssameddine, F. Neumeyer, I. Rahman, M. Deherrera, S. Ikegawa, P. Sanchez, X. Zhang, Y. Wang, J. Williams, D. Gogl, H. Xu, M. Farook, D. Aceves, H. K. Lee, F. Mancoff, M. Chou, C. Tan, B. Huang, S. Mukherjee, M. Lu, A. Shah, K. Nagel, Y. Kim, S. Aggarwal
{"title":"Persistent xSPI STT-MRAM with up to 400MB/s Read and Write Throughput","authors":"S. Alam, D. Houssameddine, F. Neumeyer, I. Rahman, M. Deherrera, S. Ikegawa, P. Sanchez, X. Zhang, Y. Wang, J. Williams, D. Gogl, H. Xu, M. Farook, D. Aceves, H. K. Lee, F. Mancoff, M. Chou, C. Tan, B. Huang, S. Mukherjee, M. Lu, A. Shah, K. Nagel, Y. Kim, S. Aggarwal","doi":"10.1109/IMW52921.2022.9779276","DOIUrl":"https://doi.org/10.1109/IMW52921.2022.9779276","url":null,"abstract":"We present the new generation of Everspin's STT-MRAM device with extended Serial Peripheral Interface (xSPI). The device is capable of persistent memory operation with random reads and writes while supporting page-buffered program and optional erase for compatibility with Serial NOR Flash protocol. MRAM technology has been optimized for the needed improvements to enable low-latency industrial applications. Two bank architecture with a new write scheme is employed for fast write providing up to 4 orders of magnitude write energy improvement over traditional NOR. We demonstrate full 64Mb die high-speed functionality with symmetric read and write throughput of up to 400MB/s.","PeriodicalId":132074,"journal":{"name":"2022 IEEE International Memory Workshop (IMW)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125440764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
1S1R sub-threshold operation in Crossbar arrays for low power BNN inference computing 用于低功耗BNN推理计算的Crossbar阵列1S1R亚阈值运算
2022 IEEE International Memory Workshop (IMW) Pub Date : 2022-05-01 DOI: 10.1109/IMW52921.2022.9779253
J. M. Lopez, F. Rummens, L. Reganaz, A. Heraud, T. Hirtzlin, L. Grenouillet, Gemma Navarro, M. Bernard, C. Carabasse, N. Castellani, V. Meli, S. Martin, T. Magis, E. Vianello, C. Sabbione, D. Deleruyelle, M. Bocquet, J. Portal, G. Molas, F. Andrieu
{"title":"1S1R sub-threshold operation in Crossbar arrays for low power BNN inference computing","authors":"J. M. Lopez, F. Rummens, L. Reganaz, A. Heraud, T. Hirtzlin, L. Grenouillet, Gemma Navarro, M. Bernard, C. Carabasse, N. Castellani, V. Meli, S. Martin, T. Magis, E. Vianello, C. Sabbione, D. Deleruyelle, M. Bocquet, J. Portal, G. Molas, F. Andrieu","doi":"10.1109/IMW52921.2022.9779253","DOIUrl":"https://doi.org/10.1109/IMW52921.2022.9779253","url":null,"abstract":"We experimentally validated the sub-threshold reading strategy in OxRAM+OTS crossbar arrays for low precision inference in Binarized Neural Networks. In order to optimize the 1S1R sub-threshold current margin, an experimental and theoretical statistical study on HfO2-based 1S1R stacks with various OTS technologies has been performed. Impact of device features (OxRAM RHRS, OTS non-linearity and OTS threshold current) on 1S1R sub-threshold reading is elucidated. Accuracy and power consumption of a Binarized Neural Network designed in 28nm CMOS have been estimated with Monte Carlo simulations. A gain of 3 orders of magnitude in power consumption is demonstrated in comparison with conventional threshold reading strategy, while preserving the same network accuracy.","PeriodicalId":132074,"journal":{"name":"2022 IEEE International Memory Workshop (IMW)","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128214131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Highly Stackable 3D Ferroelectric NAND Devices: Beyond the Charge Trap Based Memory 高度可堆叠的3D铁电NAND器件:超越基于电荷陷阱的存储器
2022 IEEE International Memory Workshop (IMW) Pub Date : 2022-05-01 DOI: 10.1109/IMW52921.2022.9779278
S. Yoon, Sung I. Hong, Garam Choi, Daehyun Kim, Ildo Kim, S. Jeon, Changhan Kim, Kyunghoon Min
{"title":"Highly Stackable 3D Ferroelectric NAND Devices: Beyond the Charge Trap Based Memory","authors":"S. Yoon, Sung I. Hong, Garam Choi, Daehyun Kim, Ildo Kim, S. Jeon, Changhan Kim, Kyunghoon Min","doi":"10.1109/IMW52921.2022.9779278","DOIUrl":"https://doi.org/10.1109/IMW52921.2022.9779278","url":null,"abstract":"In this study, we demonstrate for the first time the multi-level capable 3D ferroelectricNAND (Fe-NAND) device using the 3D NAND test vehicle for mass production. The present 3D ferroelectric NAND shows the potential multi-level cell operation with the 3.4 V program/erase window. We also reported cycling and retention characteristics.","PeriodicalId":132074,"journal":{"name":"2022 IEEE International Memory Workshop (IMW)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131531740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
[IMW 2022 Front cover] [IMW 2022封面]
2022 IEEE International Memory Workshop (IMW) Pub Date : 2022-05-01 DOI: 10.1109/imw52921.2022.9779304
{"title":"[IMW 2022 Front cover]","authors":"","doi":"10.1109/imw52921.2022.9779304","DOIUrl":"https://doi.org/10.1109/imw52921.2022.9779304","url":null,"abstract":"","PeriodicalId":132074,"journal":{"name":"2022 IEEE International Memory Workshop (IMW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129690936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
NOR Flash-based Multilevel In-Memory-Searching Architecture for Approximate Computing 基于NOR闪存的近似计算多级内存搜索体系结构
2022 IEEE International Memory Workshop (IMW) Pub Date : 2022-05-01 DOI: 10.1109/IMW52921.2022.9779250
Yu-Hsuan Lin, P. Tseng, F. Lee, Ming-Hsiu Lee, C. Hsieh, Dai-Ying Lee, Keh-Chung Wang, Chih-Yuan Lu
{"title":"NOR Flash-based Multilevel In-Memory-Searching Architecture for Approximate Computing","authors":"Yu-Hsuan Lin, P. Tseng, F. Lee, Ming-Hsiu Lee, C. Hsieh, Dai-Ying Lee, Keh-Chung Wang, Chih-Yuan Lu","doi":"10.1109/IMW52921.2022.9779250","DOIUrl":"https://doi.org/10.1109/IMW52921.2022.9779250","url":null,"abstract":"In the approximate in-memory-searching (IMS) system, the numeral-system-induced matching score counting error will cause computation error and degrade the system performance significantly especially at high resolution scenarios. This paper discusses the problem in detail and proposes a novel NOR-Flash-based multilevel IMS cell and the related operation scheme for approximate computing. The device characteristics and reliability performances are carefully evaluated on a high density NOR Flash array. Experiments and simulations suggest that the proposed approximate IMS cell not only can provide the matching score based on the difference between the input and the stored data, but also improve the system robustness toward data variation.","PeriodicalId":132074,"journal":{"name":"2022 IEEE International Memory Workshop (IMW)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121339111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IMW 2022 Schedule and Technical Program IMW 2022计划和技术计划
2022 IEEE International Memory Workshop (IMW) Pub Date : 2022-05-01 DOI: 10.1109/imw52921.2022.9779254
{"title":"IMW 2022 Schedule and Technical Program","authors":"","doi":"10.1109/imw52921.2022.9779254","DOIUrl":"https://doi.org/10.1109/imw52921.2022.9779254","url":null,"abstract":"","PeriodicalId":132074,"journal":{"name":"2022 IEEE International Memory Workshop (IMW)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123431567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
SSD Drive Failure Prediction on Alibaba Data Center Using Machine Learning 基于机器学习的阿里数据中心SSD硬盘故障预测
2022 IEEE International Memory Workshop (IMW) Pub Date : 2022-05-01 DOI: 10.1109/IMW52921.2022.9779284
Lei Chen, Zongpeng Zhu, Anyu Li, N. Mashhadi, Robert E. Frickey, Jinhe Ye, Xin Guo
{"title":"SSD Drive Failure Prediction on Alibaba Data Center Using Machine Learning","authors":"Lei Chen, Zongpeng Zhu, Anyu Li, N. Mashhadi, Robert E. Frickey, Jinhe Ye, Xin Guo","doi":"10.1109/IMW52921.2022.9779284","DOIUrl":"https://doi.org/10.1109/IMW52921.2022.9779284","url":null,"abstract":"Flash-based Solid-State Drives (SSDs) have become a critical storage tier in data centers and enterprise storage systems. Cloud companies are very interested in predicting drive failures. Drive failure prediction enables managing drive replacement and backup data beforehand and helps planning drive purchase strategies. Solidigm and Alibaba collaborate to collect and analyze Self-Monitoring, Analysis, and Reporting Technology (SMART) data and predict SSD failures 30 days ahead of time using machine learning techniques. In this paper, we use group k-fold cross-validation to select the best parameters for machine learning models and avoid overfitting. After obtaining the prediction score of each sample from the model, a post-processing with neural network is applied on those prediction scores to get the drive-level prediction. A modified ensemble learning method is designed and implemented by majority voting on different models of Light GBM and Random Forest to further improve prediction results. This paper is the first work in both academia and the storage industry to design a drive failure prediction system for deploying in data centers by optimizing models with the highest Precision instead of the highest F1-score to minimize false positive rate. We advance to get drive failure prediction with 100% Precision and 21% Recall, enabling us to avoid the high cost of false positives.","PeriodicalId":132074,"journal":{"name":"2022 IEEE International Memory Workshop (IMW)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115137448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Performance Benchmarking of Spin-Orbit Torque Magnetic RAM (SOT-MRAM) for Deep Neural Network (DNN) Accelerators 用于深度神经网络(DNN)加速器的自旋-轨道转矩磁性内存(SOT-MRAM)性能基准测试
2022 IEEE International Memory Workshop (IMW) Pub Date : 2022-05-01 DOI: 10.1109/IMW52921.2022.9779279
Yandong Luo, Piyush Kumar, Y. Liao, William Hwang, F. Xue, Wilman Tsai, Shan-Xiang Wang, A. Naeemi, Shimeng Yu
{"title":"Performance Benchmarking of Spin-Orbit Torque Magnetic RAM (SOT-MRAM) for Deep Neural Network (DNN) Accelerators","authors":"Yandong Luo, Piyush Kumar, Y. Liao, William Hwang, F. Xue, Wilman Tsai, Shan-Xiang Wang, A. Naeemi, Shimeng Yu","doi":"10.1109/IMW52921.2022.9779279","DOIUrl":"https://doi.org/10.1109/IMW52921.2022.9779279","url":null,"abstract":"In this paper, the system level evaluation is performed for DNN inference engines using SOT-MRAM, which includes compute-in-memory (CIM) paradigm and near-memory systolic array. The write performance of the SOT materials is projected to 7nm with a macrospin model. For read-intensive CIM, SOT-MRAM with increased on-resistance can achieve 51% and 93% higher energy efficiency than 8T-SRAM at 22nm and 7nm nodes, respectively. For write-intensive systolic array at 7nm node, SOT-MRAM with PtCu track shows 17% higher energy efficiency than SRAM global buffer, respectively.","PeriodicalId":132074,"journal":{"name":"2022 IEEE International Memory Workshop (IMW)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132129191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信