Yandong Luo, Piyush Kumar, Y. Liao, William Hwang, F. Xue, Wilman Tsai, Shan-Xiang Wang, A. Naeemi, Shimeng Yu
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引用次数: 0
Abstract
In this paper, the system level evaluation is performed for DNN inference engines using SOT-MRAM, which includes compute-in-memory (CIM) paradigm and near-memory systolic array. The write performance of the SOT materials is projected to 7nm with a macrospin model. For read-intensive CIM, SOT-MRAM with increased on-resistance can achieve 51% and 93% higher energy efficiency than 8T-SRAM at 22nm and 7nm nodes, respectively. For write-intensive systolic array at 7nm node, SOT-MRAM with PtCu track shows 17% higher energy efficiency than SRAM global buffer, respectively.