{"title":"Non Volatile Memory in Advanced Smart Power technology: product requirements and integration solutions","authors":"G. Croce","doi":"10.1109/IMW52921.2022.9779244","DOIUrl":"https://doi.org/10.1109/IMW52921.2022.9779244","url":null,"abstract":"The increasing complexity of chip functionality and the demand for higher configurability to service smart power requirements is driving interesting developments in emerging memories. ePCM is prominent among these for its benefits in terms of cost, process complexity, and performances. This paper begins with an overview of the existing baseline solutions (fuses, antifuses, single-poly floating gates) addressing low-density NVM application needs and more traditional floating gate memories (dual poly-flash) for higher density applications. The discussion then progresses to the promising results obtained on test chips and on real power product, which demonstrate the successful integration of PCM in the latest BCD platforms.","PeriodicalId":132074,"journal":{"name":"2022 IEEE International Memory Workshop (IMW)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114393921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Weishen Chu, Seyyed Ehsan Esfahani Rashidi, Yanli Zhang, J. Alsmeier, Toshiyuki Sega
{"title":"An Analytical Model for Thin Film Pattern-dependent Asymmetric Wafer Warpage Prediction","authors":"Weishen Chu, Seyyed Ehsan Esfahani Rashidi, Yanli Zhang, J. Alsmeier, Toshiyuki Sega","doi":"10.1109/IMW52921.2022.9779248","DOIUrl":"https://doi.org/10.1109/IMW52921.2022.9779248","url":null,"abstract":"Wafer warpage can cause severe issues in semiconductor fabrication process. In 3D Flash industry, wafer warpage control is crucial to achieve 3D NAND scaling. This study proposed an analytical model to rapidly predict the stepwise asymmetric wafer warpage in the NAND integration procedure. The impact of film pattern on wafer warpage was introduced to the model via effective material stiffness calculation. The model was validated by stepwise wafer warpage measurements, and parametric analysis was conducted to investigate the effects of key NAND design parameters on asymmetric wafer warpage.","PeriodicalId":132074,"journal":{"name":"2022 IEEE International Memory Workshop (IMW)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130308452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Lehninger, H. Mähne, T. Ali, R. Hoffmann, R. Olivo, M. Lederer, K. Mertens, T. Kämpfe, K. Biedermann, Matthias Landwehr, A. Heinig, Defu Wang, Yukai Shen, K. Bernert, S. Thiem, K. Seidel
{"title":"Integration of BEoL Compatible 1T1C FeFET Memory Into an Established CMOS Technology","authors":"D. Lehninger, H. Mähne, T. Ali, R. Hoffmann, R. Olivo, M. Lederer, K. Mertens, T. Kämpfe, K. Biedermann, Matthias Landwehr, A. Heinig, Defu Wang, Yukai Shen, K. Bernert, S. Thiem, K. Seidel","doi":"10.1109/IMW52921.2022.9779252","DOIUrl":"https://doi.org/10.1109/IMW52921.2022.9779252","url":null,"abstract":"Recently, hafnium oxide based ferroelectric memories gained great attention due to good scalability, high speed operation, and low power consumption. In contrast to the FRAM concept, the FeFET offers non-destructive read-out. However, the integration of the FeFET into an established CMOS technology entails several challenges. Herein, an 1T1C FeFET with separated transistor (1T) and ferroelectric capacitor (1C) is described and demonstrated. This alternative approach can be integrated into standard process technologies without introducing significant modifications of the front-end-of-line. All important steps starting from the integration of MFM devices into the BEoL through the fabrication and characterization of single 1T1C memory cells with various capacitor area ratios for bit cell tuning up to the initial demonstration of an 8 kbit test-array are covered.","PeriodicalId":132074,"journal":{"name":"2022 IEEE International Memory Workshop (IMW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116344762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Suryavanshi, G. Yeric, Max Irby, X. M. Huang, G. Rosendale, L. Shifren
{"title":"Extreme Temperature (> 200 °C), Radiation Hard (> 1 Mrad), Dense (sub-50 nm CD), Fast (2 ns write pulses), Non-Volatile Memory Technology","authors":"S. Suryavanshi, G. Yeric, Max Irby, X. M. Huang, G. Rosendale, L. Shifren","doi":"10.1109/IMW52921.2022.9779251","DOIUrl":"https://doi.org/10.1109/IMW52921.2022.9779251","url":null,"abstract":"We have developed an ultra-dense (sub-50 nm device diameter), ultra-fast (2 ns write pulse), non-polar, non-volatile memory that can operate at > 200°C temperatures while being immune to radiation (> 1 Mrad (SiO2)). Our technology, CeRAM, is integrated into the back-end-of-line (BEOL) 1 kb arrays and is compatible with high-temperature substrates including SiC, GaN, as well as Silicon on insulator (SOI). CeRAM can retain its memory state at 400°C for one hour bake. Such characteristics are ideal for multiple applications that include automotive, industrial mining and drilling, as well as defense and space.","PeriodicalId":132074,"journal":{"name":"2022 IEEE International Memory Workshop (IMW)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126350836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Spessot, S. Salahuddin, Ricardo Escobar, R. Ritzenthaler, Y. Xiang, Rahul Budhwani, E. Litta, E. Capogreco, J. Bastos, Yangyin Chen, N. Horiguchi
{"title":"Thermally stable, packaged aware LV HKMG platforms benchmark to enable low power I/O for next 3D NAND generations","authors":"A. Spessot, S. Salahuddin, Ricardo Escobar, R. Ritzenthaler, Y. Xiang, Rahul Budhwani, E. Litta, E. Capogreco, J. Bastos, Yangyin Chen, N. Horiguchi","doi":"10.1109/IMW52921.2022.9779308","DOIUrl":"https://doi.org/10.1109/IMW52921.2022.9779308","url":null,"abstract":"Input/Output transistor are expected to significantly improve power-performance to sustain the expected need of future 3D NAND Flash product for Big Data. In this work we present an HKMG thermally stable platform for next generation NAND I/O periphery devices. We propose a methodology to benchmark power and area device platform trade-off. Key element of the packaged product and different circuit design topologies are considered. We conclude that significant area reduction in the critical driver area combined with power saving can be achieved, providing guidelines for memory designers and system architect of next generation NAND products","PeriodicalId":132074,"journal":{"name":"2022 IEEE International Memory Workshop (IMW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130114607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"3D NAND Flash Status and Trends","authors":"L. Heineck, Jin Liu","doi":"10.1109/IMW52921.2022.9779282","DOIUrl":"https://doi.org/10.1109/IMW52921.2022.9779282","url":null,"abstract":"NAND flash has become the choice of storage media as the world enters the era of digital transformation and artificial intelligence. The request to keep NAND on a sustainable scaling path has never been stronger. In this paper, the status and the trend for NAND scaling, which includes both the array scaling as well as the CMOS scaling, are reviewed. The knobs that govern both array and CMOS scaling are introduced. The tradeoffs among the knobs are considered. System performance and its requirements to NAND scaling is also discussed. Finally, the paper ends with a conclusion that there is a path for both cost and performance scaling well into the next decade with current gate all around (GAA) architecture.","PeriodicalId":132074,"journal":{"name":"2022 IEEE International Memory Workshop (IMW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130117430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Non-volatile Memory Application to Quantum Error Correction with Non-uniformly Quantized CiM","authors":"Yuya Ichikawa, A. Goda, C. Matsui, K. Takeuchi","doi":"10.1109/IMW52921.2022.9779280","DOIUrl":"https://doi.org/10.1109/IMW52921.2022.9779280","url":null,"abstract":"Non-volatile memory (NVM)-based Computation-in-Memory (CiM) decoder is proposed for Quantum Error Correction (QEC). When the QEC circuitry is placed at cryogenic temperature, the power and area budgets are limited in order to save the cooling power. Compared with the SRAM-based CiM, NVMs have the advantage of saving memory size, power consumption, and data transfer to load the weights. Through the investigation on bit error rate (BER) tolerance, it is revealed that the accuracy of QEC can be maintained even with the high weight BER (up to 0.3%), opening the door to NVM application to QEC. In addition, two types of non-uniform weight quantization schemes (gate focused and layer focused) are proposed through the comprehensive investigation on bit-precision sensitivity. In the proposed schemes, the memory size is reduced by over 40% compared with the uniformly quantized CiM.","PeriodicalId":132074,"journal":{"name":"2022 IEEE International Memory Workshop (IMW)","volume":"249 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122942109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hitomi Tanaka, Yuta Aiba, T. Maeda, Kensuke Ota, Y. Higashi, K. Sawa, F. Kikushima, Masayuki Miura, T. Sanuki
{"title":"Toward 7 Bits per Cell: Synergistic Improvement of 3D Flash Memory by Combination of Single-crystal Channel and Cryogenic Operation","authors":"Hitomi Tanaka, Yuta Aiba, T. Maeda, Kensuke Ota, Y. Higashi, K. Sawa, F. Kikushima, Masayuki Miura, T. Sanuki","doi":"10.1109/IMW52921.2022.9779301","DOIUrl":"https://doi.org/10.1109/IMW52921.2022.9779301","url":null,"abstract":"In this paper, it is shown that the combination of single-crystal channel and cryogenic operation at 77 K using liquid nitrogen improves the cell transistor characteristics and the storage performance of 3D Flash memory. Compared to the cryogenic operation with poly-Si channels, that we have already reported, the cryogenic operation with single-crystal channels results in a steepening of the cell transistor subthreshold slope and reduced read noise. In particular, read noise is significantly suppressed to one-third due to the synergistic effect of the improvement by single-crystal and the cryogenic operation, compared with poly-Si channel in room temperature. Furthermore, data retention is improved at cryogenic temperature compared to room temperature. These improvements lead to a narrower Vth distribution of the cell, which enables bit-cost scaling through a multi-level cell. An ultra-multi-level cell of 7 bits per cell is successfully demonstrated for the first time, and its feasibleness in future storage products is shown.","PeriodicalId":132074,"journal":{"name":"2022 IEEE International Memory Workshop (IMW)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114461282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Raffel, R. Olivo, M. Lederer, F. Müller, R. Hoffmann, T. Ali, K. Mertens, L. Pirro, M. Drescher, S. Beyer, T. Kämpfe, K. Seidel, L. Eng, J. Heitmann
{"title":"Endurance improvements and defect characterization in ferroelectric FETs through interface fluorination","authors":"Y. Raffel, R. Olivo, M. Lederer, F. Müller, R. Hoffmann, T. Ali, K. Mertens, L. Pirro, M. Drescher, S. Beyer, T. Kämpfe, K. Seidel, L. Eng, J. Heitmann","doi":"10.1109/IMW52921.2022.9779277","DOIUrl":"https://doi.org/10.1109/IMW52921.2022.9779277","url":null,"abstract":"HfO2-based ferroelectric FETs (FeFETs) offer excellent retention, scalability, and memory window. However, achieving high endurance is still challenging. Here, a fluorination treatment is presented that enables significant endurance and device stability improvement. Noise and charge pumping methods are applied to obtain deeper understanding of the underlying defect interaction in FeFETs.","PeriodicalId":132074,"journal":{"name":"2022 IEEE International Memory Workshop (IMW)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127270976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}